EP80579 Datasheet, PDF (1614/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Note:
pin will not be stored. This mode can be used to test, through software, whether or not
the Transmit FIFO or the Receive FIFO operates properly as a first-in-first-out memory
stack.
When this mode is enabled, a write followed immediately by a read to the RX or TX
FIFOs may not return the correct read data. Since this is a test mode, a delay should be
inserted between the write and read transactions so that the data is guaranteed to be
read back correctly.
40.4.2.11 Select FIFO for Enable FIFO Write/Read (STRF)
This bit selects whether the Transmit or Receive FIFO is enabled for write/read.
40.4.3 SSP Status Register
40.4.3.1 Offset 08h: SSSR - SSP Status Register Details
The SSP status register (SSSR) contains bits that signal overrun errors as well as the
transmit and receive FIFO service requests. Each of these hardware-detected events
signal an interrupt request to the interrupt controller. The status register also contains
flags that indicate when the SSP is actively transmitting characters, when the transmit
FIFO is not full, and when the receive FIFO is not empty (no interrupt generated).
Bits that cause an interrupt will signal the request as long as the bit is set. Once the bit
is cleared, the interrupt is cleared. Read/write bits are called status bits, read-only bits
are called flags. Status bits are referred to as “sticky” (once set by hardware, must be
cleared by software). Writing a 1 to a sticky status bit clears it, writing a 0 has no
effect. Read-only flags are set and cleared by hardware; writes have no effect.
Additionally some bits that cause interrupts have corresponding mask bits in the
control registers and are indicated in the section headings that follow.
Register Name:
SSSR
Block
Base Address:
N/A
Offset Address
08h
Reset Value 0000F024
Register Description: SSP Status Register
Access: (See below.)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
RFL
TFL
Rsvd.
Table 40-5. Offset 08h: SSSR - SSP Status Register Details (Sheet 1 of 2)
Description:
View: PCI
BAR: CSRBAR
Bus:Device:Function: M:6:0
Offset Start: 08h
Offset End: 0Bh
Size: 32 bit
Default: 0000F004h
Power Well: Core
Bit Range
31 :16
15 :12
11 :08
Bit Acronym
Bit Description
Reserved
RFL
TFL
Reserved
Receive FIFO Level:
Number of entries in Receive FIFO
Transmit FIFO Level:
Number of entries in Transmit FIFO
Sticky
Bit Reset
Value
0h
Fh
Bit Access
RV
RO
0h
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
1614
August 2009
Order Number: 320066-003US