EP80579 Datasheet, PDF (309/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
12.1.2
— 32-bit addressing range on the Memory Mapped I/O Subsystem Interface (no
NSI access)
• Maximum transfer of 16 MB transfers per descriptor
• Fully programmable by the IA-32 core
— Configuration space mapping for EDMA engine capability and control
— Memory-mapped space for EDMA channel-specific register sets
• Chain Mode EDMA transfer with automatic data chaining for scattering/gathering of
data blocks
— EDMA chaining continued until a “null” descriptor pointer is encountered
— Support for appending a block to the end of current EDMA chain
— Automated descriptor retrieval from local memory during chaining – single read
• Programmable independent alignment between source and destination
— Byte aligned transfer on the local system memory interface
— Byte aligned transfer on the I/O subsystem interface
• Support for non-coherent transfers both to and from system memory on a per
descriptor basis
— Independent control of coherency for source and destination
• Programmable support for interrupt generation on block–by-block basis
— Selectable MSI or legacy level-sensitive interrupt function
— End of current block transfer
— End of current chain
— For any error causing a transfer to abort
• Increment of the source and destination address for standard transfers
• Increment of the destination and decrement of the source address to enable byte
stream reversal
• Constant address mode for the destination address based on the transfer
granularity to enable targeting of memory mapped I/O FIFO devices
• Buffer/memory initialization mode
Logical Block Diagram
Figure 12-2 shows the conceptual interface of the EDMA channels to different l
interfaces.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
309