EP80579 Datasheet, PDF (888/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
23.6.2.2 Error Recovery
23.6.2.2.1 HBA Aborting a Transfer
When the HBA detects an error that it cannot recover from, it may need to end the
transfer on the SATA interface.
To do this, the HBA asserts SYNC Escape to stop the bad FIS, and when the device is
quiescent, returns to idle. The SATA device should send a D2H Register FIS at this
point, with the ERR bit set to indicate an error in the transfer.
When aborting a transfer, the HBA does not wait for the D2H Register FIS before
proceeding with error recovery (such as setting interrupt status bits and generating
interrupts). This is because a device may be in a hung condition and cannot generate
the D2H Register FIS.
23.6.2.2.2 Software Error Recovery
When an interrupt is generated due to an error condition, software will attempt to
recover. Fatal errors (signified by the setting of PxIS.HBFS, PxIS.HBDS, PxIS.IFS, or
PxIS.TFES) will cause the HBA to enter the ERR:Fatal state, and clear PxCMD.CR. In
this state, the HBA shall not issue any new commands nor acknowledge DMA Setup
FISes to process any native command queuing commands. To recover, the port must be
restarted; the port is restarted by clearing PxCMD.ST to '0' and then setting PxCMD.ST
to '1'. For non-fatal errors (signified by the setting of PxIS.INFS or PxIS.OFS) the HBA
continues to operate.
If the transfer was aborted, the device is expected to send a D2H Register FIS with
PxTFD.STS.ERR set to '1' and both PxTFD.STS.BSY and PxTFD.STS.DRQ cleared to '0'.
Under this scenario, system software knows that the device is in a stable state and
transfers may be restarted without issuing a COMRESET to the device. No FIS will be
posted and no register updates will be done based on FISes received after a fatal error
has occurred. Received FISes will not be acted on until a COMRESET or a new
command is sent to the device, after the error is recovered from appropriately including
clearing the PxCMD.ST bit.
For fatal errors, software must determine which commands were not processed and
either re-issue them or notify higher level software that the command failed.
To detect an error that requires software recovery actions to be performed, software
should check whether any of the following status bits are set on an interrupt:
PxIS.HBFS, PxIS.HBDS, PxIS.IFS, and PxIS.TFES. If any of these bits are set, software
should perform the appropriate error recovery actions based on whether non-queued
commands were being issued or native command queuing commands were being
issued.
23.6.3
Hot Plug Operation
If HCAP.SIS is set, the SATA controller uses the SATAGP[3:0] pins as interlock switches.
The EP80579 supports Hot Plug Surprise Removal Notification. However Hot Plug
Surprise Removal Notification (without an interlock switch) is mutually exclusive with
the PARTIAL and SLUMBER power management states.
Intel^® EP80579 Integrated Processor Product Line Datasheet
888
August 2009
Order Number: 320066-003US