EP80579 Datasheet, PDF (1461/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 37-41. IMC0: Interrupt 0 Mask Clear Register (Sheet 2 of 2)
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 00D8h
Offset End: 00DBh
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 00D8h
Offset End: 00DBh
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 00D8h
Offset End: 00DBh
Size: 32 bits
Default: 00000000h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range
22
21
20
19 : 17
16
15
14 : 8
07
06
05
04
03
02
01
00
Bit Acronym
Bit Description
Sticky
Rsvd
ERR_TXDS
ERR_RXDS
Rsvd
SRPD
TXD_LOW
Rsvd
RXT0
RXO
Rsvd
RXDMT0
Rsvd
Rsvd
TXQE
TXDW
Reserved
Clears the mask for DMA Transmit Descriptor Buffer ECC
Error
Clears the mask for DMA Receive Descriptor Buffer ECC
Error
Reserved
Clears the mask for Small Receive Packet Detected and
Transferred
Clears the mask for Transmit Descriptor Low Threshold Hit
Reserved
Clears the mask for Receiver Timer Interrupt
Clears the mask for Receiver Overrun. Set on receive data
FIFO overrun
Reserved
Clears the mask for Receive Descriptor Minimum Threshold
hit
Reserved
Reserved. Must be written as ‘0’
Clears the mask for Transmit Queue Empty
Clears the mask for Transmit Descriptor Written Back
Bit Reset
Value
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
Bit Access
RV
WO
WO
RV
WO
WO
RV
WO
WO
RV
WO
WO
RV
WO
WO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1461