EP80579 Datasheet, PDF (485/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-91. Offset 82h: DRAM_NERR - DRAM Next Error Register (Sheet 2 of 2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:1
Offset Start: 82h
Offset End: 83h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
03
02
01
00
Bit Acronym
Bit Description
Sticky
ETDA
USDEA
URMEA
CRMEA
Error Threshold Detect: This bit is sticky through reset.
System software clears this bit by writing a 1 to the
location. This bit can be set by either a SEC or DED event,
if the corresponding error counter is set. The bit can also
set if the DRAM_SEC current error count register is
cleared, via a software diagnostic error count write.
Y
0 = No Error Threshold detected
1 = Error Threshold detected.
(NON-FATAL)
Uncorrectable Scrubber Data Error: This bit is sticky
through reset. System software clears this bit by writing a
1 to the location.
0 = No Scrubber Error Detected
Y
1 = Scrubber Error Detected.
(NON-FATAL)
Uncorrectable Read Memory Error: (Uncorrectable)
Applies to non-scrub demand (normal demand fetch)
reads. This bit is sticky through reset. System software
clears this bit by writing a 1 to the location.
0 = No Uncorrectable Non-Scrub Demand Read Memory
Y
Error
1 = Uncorrectable Non-Scrub Demand Read Memory Error.
(NON-FATAL)
Correctable read memory Error: (Correctable) SECs
(Single Bit Error Correction) detected by normal demand
requests or scrub/demand fetch (normal read to memory).
This bit is sticky through reset. System software clears this
bit by writing a 1 to the location.
Y
0 = No Correctable Read Memory Error.
1 = Correctable Read Memory Error.
(NON-FATAL)
Bit Reset
Value
0b
0b
0b
0b
Bit Access
RWC
RWC
RWC
RWC
16.2.1.38 Offset 84h: DRAM_EMASK - DRAM Error Mask Register
This register masks the DRAM Controller errors and events from being recognized,
preventing them from being logged at either the unit level (via the DRAM_FERR or
DRAM_NERR registers, see Section 16.2.1.36, “Offset 80h: DRAM_FERR - DRAM First
Error Register” and Section 16.2.1.37, “Offset 82h: DRAM_NERR - DRAM Next Error
Register”) or global level (via GLOBAL_FERR or GLOBAL_NERR)and preventing an
interrupt/messages from being generated.
These bits are sticky through reset.
Note:
If ETD_MASK is changed from 0 to 1 and any error count is already above threshold,
then the error(s) will be immediately reported via FERR/NERR.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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