EP80579 Datasheet, PDF (362/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
devices, and is logged by the IMCH as a “Link Down” error. If escalation of this event is
enabled, software is notified of the link DL_DOWN condition. Once software has to be
involved, then data will likely be lost, and processes need to be restarted, but this is
still preferred to having to shut the system down, or go offline for an extended period
of time.
14.1.4 Test/Support Major Buses
14.1.4.1
14.1.4.2
14.1.4.3
14.1.4.4
IICH XOR
The IICH supports XOR chain test mode. This non-functional test mode is a dedicated
test mode when the chip is not operating in its normal manner.
SMB (IMCH)
Full access to internal configuration registers via the System Management Bus is
supported. This will allow a server management card to control system configuration
and to read various error/status information. Accesses to devices marked as not
present will still be possible through SMB.
SMB (IICH)
The IICH SMB is SMBus 2.0 compliant and it is compatible with most 2-wire
components that are also I2C compatible. The host interface allows IA-32 core to
communicate via SMBus, the slave interface allows external microcontroller to access
system resource in IICH. This IICH SMB does not support access to internal
configuration registers.
I²C
Access to the external DIMMs will be through the IICH, via I²C. This will be used to
determine the nature of the DIMMs present in order to configure the memory
subsystem correctly.
14.2
Exception Handling
There are a variety of exception conditions. Some are internally detected; some are
detected on input pins; some are passed on behalf of other devices. All recognized
exceptions eventually cause the IMCH to do one of the following: Send a SERR
message, send a SCI message to the IICH, send a SMI message to the IICH, assert
MCERR# on the front side bus, or do nothing. There is no determination of which errors
go to which of the three error message schemes; it merely provides the capability for
all combinations. It is the responsibility of the BIOS to determine the ultimate error
reporting scheme. There will be an attempt to classify errors to whether they are fatal
or non-fatal to more closely match the enterprise error presentation.
14.2.1 FERR/NERR Global Register Scheme
Figure 14-1. Global FERR/NERR Register Representation
Fatal (14b)
Non-Fatal (14b)
Reserved (4b)
The Global FERR register consists of three fields. The first or fatal field has 14b
indicates the first signaled fatal global error from 14 different units. The second or non-
fatal field indicates the first non-fatal global error that occurs from the same 14
different units. A non-fatal error may be either correctable or uncorrectable, but not
Intel^® EP80579 Integrated Processor Product Line Datasheet
362
August 2009
Order Number: 320066-003US