EP80579 Datasheet, PDF (313/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
It is possible but unexpected that the source and destination address ranges defined by
chain descriptors may overlap in physical memory. While there are scenarios where this
may produce no errors in the resulting memory image, the software must ensure that
no failure results from such usage. Hardware checks are not built into the EDMA
mechanism to ensure that source and destination physical address ranges do not
overlap. Similarly, there are no hardware interlocks to ensure that independent
channels are not programmed to modify the same address range simultaneously. If
software were to create such a situation, the resultant memory image would be
indeterminate, since there are no guarantees as to the relative access ordering among
simultaneously active channels.
Figure 12-4. Chaining Mechanism
Next Descriptor Address Register (32 -bit or 64-bit)
Source Address (SAR)
Source Upper Address (SUAR)
Destination Address (DAR)
Destination Upper Address (DUAR)
Next Descriptor Address (NDAR)
Next Descriptor Upper Address (NDUAR)
Transfer Count (TCR)
Descriptor Control (DCR)
Linked
Descriptors in
Memory
First
Block
Transfer
Source Address (SAR)
Source Upper Address (SUAR)
Destination Address (DAR)
Destination Upper Address (DUAR)
Next Descriptor Address (NDAR)
Next Descriptor Upper Address (NDUAR)
Transfer Count (TCR)
Descriptor Control (DCR)
Second
Block
Transfer
Source Address (SAR)
Source Upper Address (SUAR)
Destination Address (DAR)
Destination Upper Address (DUAR)
Next Descriptor Address (NDAR)
Next Descriptor Upper Address (NDUAR)
Transfer Count (TCR)
Descriptor Control (DCR)
Nth Block
Transfer
End of Chain
(Null Value)
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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