EP80579 Datasheet, PDF (923/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 24-38. Process Call Protocol without PEC
57 – 64 Data Byte High from slave - 8 bits
65 NOT acknowledge
66 Stop
The order sent with PEC enabled is shown in Table 24-39.
Table 24-39. Process Call Protocol with PEC
Bit
Description
1
Start
2 – 8 Slave Address - 7 bits
9
Write
10 Acknowledge from Slave
11 – 18 Command code - 8 bits
19 Acknowledge from slave
20 – 27 Data byte Low - 8 bits
28 Acknowledge from Slave
29 – 36 Data Byte High - 8 bits
37 Acknowledge from slave
38 Repeated Start
39 – 45 Slave Address - 7 bits
46 Read
47 Acknowledge from slave
48 – 55 Data Byte Low from slave - 8 bits
56 Acknowledge
57 – 64 Data Byte High from slave - 8 bits
65 Acknowledge
66 – 73 PEC from slave
74 NOT acknowledge
75 Stop
24.4.2.6
Block Read/Write
The CMI contains a 32-byte buffer for read and write data which can be enabled by
setting bit ‘1’ of the Auxiliary Control register at offset 0Dh in I/O space, as opposed to
a single byte of buffering. This 32-byte buffer is filled with write data before
transmission and filled with read data on reception. In the CMI, the interrupt is
generated only after a transmission or reception of 32 bytes, or when the entire byte
count has been transmitted/received.
The block write command with I2C_EN set and either the PEC_EN or AAC bit set
produces undefined results. Software must either force the I2C_EN bit or both PEC_EN
and AAC bits to 0 when running this command.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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