EP80579 Datasheet, PDF (890/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Figure 23-4. Power State Hierarchy
Power
HBA = D0
Device = D0
PHY =
Ready
PHY = PHY =
Partial Slumber
Device = D1 Device = D3
PHY =
Slumber
(see note)
PHY =
Slumber
(see note)
HBA = D3
Device = D3
PHY =
Slumber
(see note)
Resume Latency
Note:
The Phy is not required to be in a Slumber state when the device is in a D1 or D3 state,
nor is it required to be in a Slumber state when the HBA is in a D3 state. While this may
be the likely condition of the interface when the devices connected to the interface are
in a low power state, it is not a requirement, and the interface shall break out of these
states on a power management event.
23.6.4.3 Power State Transitions
23.6.4.3.1 Interface Power Management
The Serial ATA 1.0a Specification defines two lower power interface power
management states, Partial and Slumber, in order to save power on the Serial ATA link
in power sensitive systems. The Partial and Slumber interface power management
states can be initiated by software, the HBA itself, or by the device. The interface power
management state is negotiated between the host and the device on the interface
using Serial ATA primitives. Any request can be accepted (using the PMACK primitive)
or rejected (using PMNACK primitives) based upon current conditions and settings in
the device and HBA. The current interface power management state is reflected to
software in PxSSTS.IPM.
Device Initiated
By default, a device that supports initiating interface power management states has
the capability disabled. To enable this feature, the appropriate SET FEATURES
command may be issued to the device. The HBA shall respond to device initiated power
management requests as specified by PxSCTL.IPM. A request from the device to enter
an interface power management state may be rejected by the HBA if the HBA needs to
transmit a FIS to the device.
System Software Initiated
PxCMD.ICC is used by system software to initiate interface power management state
transitions. The request to transition to a different interface power management state
shall only be acted on by the HBA if the Link layer is currently in the L_IDLE state. If
the HBA's Link layer is not in the L_IDLE state when the PxCMD.ICC field is written, the
request shall be ignored. The HBA shall not perform a transition directly from Partial to
Slumber or from Slumber to Partial based on a new value being written to PxCMD.ICC.
If the link is currently in a Partial or Slumber interface power management state, it is
software's responsibility to bring the link to the active state before requesting a
Intel^® EP80579 Integrated Processor Product Line Datasheet
890
August 2009
Order Number: 320066-003US