EP80579 Datasheet, PDF (846/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
23.1.7.5 Offset E4h: BFTD1 – BIST FIS Transmit Data 1 Register
Table 23-40. Offset E4h: BFTD1 – BIST FIS Transmit Data 1 Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:2
Offset Start: E4h
Offset End: E7h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 00
Bit Acronym
Bit Description
Sticky
DATA
Data (DATA): The data programmed into this register
will form the contents of the second DW of any BIST FIS
initiated by the SATA controller. This register is not port
specific – its contents will be used for BIST FIS initiated on
any port. Although the 2^nd and 3^rd DWs of the BIST FIS
are only meaningful when the “T” bit of the BIST FIS is set
to indicate “Far-End Transmit mode”, this register’s
contents will be transmitted as the BIST FIS 2^nd DW
regardless of whether or not the T bit is indicated in the
BFCS register.
Bit Reset
Value
00000000h
Bit Access
RW
23.1.7.6 Offset E8h: BFTD2 – BIST FIS Transmit Data 2 Register
Table 23-41. Offset E8h: BFTD2 – BIST FIS Transmit Data 2 Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:2
Offset Start: E8h
Offset End: EBh
Size: 32 bit
Default: 0h
Power Well: Core
Bit Range
31 : 00
Bit Acronym
Bit Description
Sticky
DATA
Data (DATA): The data programmed into this register
will form the contents of the third DW of any BIST FIS
initiated by the SATA controller. This register is not port
specific – its contents will be used for BIST FIS initiated on
any port. Although the 2^nd and 3^rd DWs of the BIST FIS
are only meaningful when the “T” bit of the BIST FIS is set
to indicate “Far-End Transmit mode”, this register’s
contents will be transmitted as the BIST FIS 3^rd DW
regardless of whether or not the “T” bit is set in the BFCS
register.
Bit Reset
Value
0h
Bit Access
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
846
August 2009
Order Number: 320066-003US