EP80579 Datasheet, PDF (363/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
14.2.1.1
14.2.1.2
fatal. These two fields usually have at most one bit asserted in each field. In the event
of simultaneous errors occurring in the same core clock, more than one bit in a field
may be set. The third 4-bit field is reserved for future enhancements.
The Global NERR register consists of these same three fields with slightly different
functionality. Instead of just the first fatal or non-fatal global errors recorded, this
register indicates the second, third, fourth, etc. global errors that are reported by the
IMCH.
These two registers do not indicate what the error was, they just indicate the severity
of the error and what unit has more specific error information.
FERR/NERR Unit Registers
Each major unit will have a minimum of a pair of registers, known as the first error
(FERR) and next error (NERR). Each unit has different and specific error bit definitions,
and provides the specific type of error; information that is not found in the global
registers. It is important to note that the unit FERR/NERR registers are simpler than the
global for purposes of reuse and ease of implementation. While the global FERR
register has a fatal and a non-fatal field, which lock down separately, the unit FERR
register only has one field. The unit is however still required to send out separate fatal
and non-fatal indications to the global FERR register if they detect both classifications
of errors. Some units will support only one type. A unit that doesn’t detect errors would
not support either type.
Clearing FERR/NERR Registers
The following write-up is the recommended guideline to minimize the loss of errors
information.
For a given FERR/NERR register pair, the FERR is read and then cleared first, and
followed by the NERR. This sequence is true for either the global FERR/NERR register
pair or any given unit. Any errors occurring after the FERR is cleared will then cause the
FERR to have a non-zero value.
After the global FERR/NERR register pair is cleared, the unit FERR/NERR register pairs
are interrogated, but only those indicated by the global FERR/NERR registers. Once the
unit pair has been cleared, the unit FERR can be read again to ensure that no errors
occurred during this local unit sequence. After the first unit FERR/NERR register pair
has been serviced, this same sequence is performed for all other unit FERR/NERR
register pairs that indicated errors in the global FERR/NERR registers. Once all unit
error registers have been serviced, the final step is to read the global FERR register to
determine if all system errors have been serviced. It is possible that errors could have
occurred for a particular unit after that unit was serviced during the error routine, or
that a unit had errors after the reading of the global FERR/NERR registers.
When clearing errors, software must clear all the FERR/NERR bits in the local interface
registers before clearing the global FERR/NERR registers. If the local registers are not
cleared first, then the global FERR/NERR registers will latch the same error again as
soon as they are cleared. This implementation allows software to clear the local FERR/
NERR registers, and then go clear the global FERR/NERR. S/W then reads back the
global FERR/NERR and if it is non-zero, then a new error has occurred. If the global
FERR/NERR has no bits set, then there are no more system errors.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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