EP80579 Datasheet, PDF (557/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.4.1.45 Offset 68h: PEADEVCAP - PCI Express* Device Capabilities Register
This register identifies the device capabilities for PCI Express*.
Table 16-184.Offset 68h: PEADEVCAP - PCI Express Device Capabilities Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 68h
Offset End: 6Bh
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 68h
Offset End: 6Bh
Size: 32 bit
Default: 00000001h
Power Well: Core
Bit Range
31 : 28
27 : 26
25 : 18
17 : 06
05
04 : 03
02 : 00
Bit Acronym
Bit Description
Sticky
Reserved
CSPLS
CSPLV
Reserved
ETFS
PFS
MPSS
Reserved
Captured Slot Power Limit Scale (Upstream Ports
Only): Specifies the scale used for the Slot Power Limit
Value.
00b = 1.0x (25.5 – 255)
01b = 0.1x (2.55 – 25.5)
10b = 0.01x (0.255 – 2.55)
11b = 0.001x (0.0 – 0.255)
Captured Slot Power Limit Value (Upstream Ports
Only): In combination with the Slot Power Limit Scale
value, this register specifies the upper limit on power
supplied by slot. Power limit (in watts) calculated by
multiplying the value in this field by the value in the Slot
Power Limit Scale field. This value is set by the
Set_Slot_Power_Limit.
Reserved
Extended Tag Field Supported: Hardwired to 0b,
indicating 5 bits, as required for a Root port.
Phantom Functions Supported: Hardwired to 00b as
required for Root ports, indicating that devices may
implement all function numbers.
Note:
Max Payload Size Supported: Hardwired to
001b to indicate a maximum 256B payload size.
Note that this refers to an inbound payload size,
since the outbound payload size is restricted to a
cacheline size to a value of 64 B.
Bit Reset
Value
0h
00b
00h
000b
0b
00b
001b
Bit Access
RO
RO
RO
RO
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
557