EP80579 Datasheet, PDF (1438/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.2
37.6.2.1
General Registers: Detailed Descriptions
CTRL – Device Control Register
This register, as well as the Extended Device Control Register (CTRL_EXT), controls the
major operational modes for the device. While software write to this register to control
device settings, several bits (such as FD and SPEED) may be overridden depending on
other bit settings and the resultant link configuration determined by the Auto-
Negotiation resolution with the PHY. See “Physical Layer Auto-Negotiation & Link Setup
Features” on page 1394 for a detailed explanation on the link configuration process.
Table 37-25. CTRL: Device Control Register (Sheet 1 of 3)
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 0000h
Offset End: 0003h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 0000h
Offset End: 0003h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 0000h
Offset End: 0003h
Size: 32 bits
Default: 00000A09h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range
31
30
29
28
27
Bit Acronym
Bit Description
Sticky
Rsvd
VME
Rsvd
TFCE
RFCE
Reserved
VLAN Mode Enable.
0 = VLAN Mode Disabled.
1 = VLAN Mode Enabled. All packets transmitted have an
802.1q header added to the packet. The contents of
the header come from the transmit descriptor and
from the VLAN type register. On receive, VLAN
information is stripped from 802.1q packets. See
“802.1q VLAN Support” on page 1400 for more
details.
Reserved
Transmit Flow Control Enable.
0 = Transmit Flow Control Disabled.
1 = Transmit Flow Control Enabled. Flow control
packets (XON & XOFF frames) will be transmitted
based on receiver fullness. If Auto-Negotiation is
enabled, this bit is set to the negotiated duplex value.
See “Physical Layer Auto-Negotiation & Link Setup
Features” on page 1394 for more information about
Auto-Negotiation.
Receive Flow Control Enable.
0 = Receive Flow Control Disabled.
1 = Receive Flow Control Enabled. Indicates the device
will respond to the reception of flow control packets.
Reception of flow control packets requires the correct
loading of the FCAH/FCAL & FCT registers. If Auto-
Negotiation is enabled, this bit is set to the negotiated
duplex value. See “Physical Layer Auto-Negotiation &
Link Setup Features” on page 1394 for more
information about Auto-Negotiation.
Bit Reset
Value
0h
0h
0h
0h
0h
Bit Access
RV
RW
RV
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
1438
August 2009
Order Number: 320066-003US