EP80579 Datasheet, PDF (709/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 17-28. Offset 3414h: BUC - Backed Up Control Register (Sheet 2 of 2)
Description:
View: PCI
BAR: RCBA
Bus:Device:Function: 0:31:0
Offset Start: 3414h
Offset End: 3417h
Size: 8 bit
Default: Variable
Power Well: Core
Bit Range
02
01
00
Bit Acronym
Bit Description
Sticky
CBE
Reserved
TS
CPU BIST Enable:
0 = The INIT# signal is not driven active when CPURST#
is active.
1= The INIT# signal is driven active when CPURST# is
active. INIT# goes inactive with the same timings as the
other CPU Interface signals (hold time after CPURST#
inactive). This bit is in the resume well and is reset by
RSMRST#, but not PCIRST# nor CF9h writes.
Reserved
Top Swap:
0 = IICH does not invert A16.
1 = IICH inverts A16 for cycles going to the BIOS space
(but not the feature space) in the FWH.
If the IICH is strapped for Top-Swap (GNT[6]# is low at
rising edge of PWROK), then this bit cannot be cleared by
software. The strap jumper must be removed and the
system rebooted.
Bit Reset
Value
0h
0h
Strap
Bit Access
RW
RW
17.1.6.5
Offset 3418h: FD - Function Disable Register
When disabling USB1 host controllers, the USB 2.0 EHCI Structural Parameters
Registers must be updated with coherent information in “Number of Companion
Controllers” and “N_Ports” fields.
When disabling a function, only the configuration space is disabled. Software must
ensure that all functionality within a controller that is not desired (such as memory
spaces, I/O spaces, and DMA engines) is disabled prior to disabling the function.
Table 17-29. Offset 3418h: FD - Function Disable Register (Sheet 1 of 2)
Description:
View: PCI
BAR: RCBA
Bus:Device:Function: 0:31:0
Offset Start: 3418h
Offset End: 341Bh
Size: 32 bit
Default: 00000080h
Power Well: Core
Bit Range
31 : 20
19
18
17
16
15
Bit Acronym
Bit Description
Reserved
Reserved
Reserved
Reserved
Reserved
U2D
Reserved
Reserved
Reserved
Reserved
Reserved
USB 2.0 Disable:
0 = The USB 2.0 host controller is enabled.
1 = The USB 2.0 host controller is disabled.
Sticky
Bit Reset
Value
0h
0h
0h
0h
0h
Bit Access
RO
RO
RO
RO
RO
0h
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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