EP80579 Datasheet, PDF (331/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
12.7.3
12.8
12.8.1
Addressing errors are fatal and will result in a EDMA channel abort, logged in CSR bit 4.
The channel response to data errors is configurable; the channel may be programmed
to abort, or to propagate the bad data to its destination.
I/O Interface Error
The following errors may be reported for a EDMA initiated access (write) on an I/O
interface:
• Address crossed into a memory destination range (checked on each write access)
• Address crossed to a new destination port during a transfer (checked at 4 KB
boundaries)
The latter error will result if poorly formed destination descriptor information specifies a
length plus address combination that crosses the addressing boundary between
independent outbound ports on the I/O subsystem. Any transfer with a destination
range crossing an aligned 4 KB boundary in address space may encounter this error.
Addressing errors are fatal and will result in a channel abort. Channel response to data
errors is configurable; each channel may be programmed to abort, or to propagate the
corrupt data to its destination.
Channel Arbitration
Arbitration among the four independent channels occurs in two stages. Each channel
has an independent bus request/grant pair to the arbiter internal to the controller. The
controller in turn has a single request/grant pair to the main arbiter. The arbiter within
the controller handles the fairness among channels, while the inbound/outbound
arbiter handles fairness between the EDMA channels and other competing traffic
sources.
The internal arbiter uses a strict round-robin policy, with the added modification of an
optional “high priority” designation for one channel at any given time. Thus a set of
competing channels will achieve balanced bandwidth performance during normal
operation.
The inbound/outbound arbiter provides a programmable single or double “grant
duration” for the EDMA controller. Thus the channel that “wins” internal arbitration may
be allowed to issue one or two access requests back-to-back in a single arbitration
cycle. The second request is accepted if the inbound/outbound arbiter is programmed
to a grant count of 2 the requesting channel has two consecutive requests of the same
type targeting the same destination ready to send, and there are sufficient command
and data resources available for the second request.
Normal Arbitration Scheme
A fully connected round-robin arbiter provides a distinctive balanced service among
competing requestors. Each of the actively competing channels will receive an equal
fraction of the bandwidth service provided by the inbound/outbound arbiter on behalf
of each EDMA channel. In the absence of any competition from the IA-32 core, PCI
Express ports, or other I/O, each EDMA channel will be allowed to saturate the memory
interface. For example, given a memory interface “saturation point” of 4 GB/s, the
round-robin scheme would be equally distributed between the competing EDMA
channels.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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