EP80579 Datasheet, PDF (1451/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.2.9
Note:
Note:
FCT – Flow Control Type Register
Flow control packets are defined by 802.3X to be either a unique multicast address or
the station address with the EtherType field indicating PAUSE. The FCAH and FCAL
registers provide the value hardware compares incoming packets against to determine
that it should PAUSE its output. This register contains the type field hardware matches
against to recognize a flow control packet.
Any packet matching the contents of {FCAH, FCAL, FCT} when CTRL.RFCE is set will be
acted on by the EP80579’s GbE. Whether flow control packets are passed to the
software depends on the state of the RCTL.DPF bit and whether the packet matches
any of the normal filters.
At the time of the original implementation, the flow control type field was not defined
and thus hardware provided programmability. Since then, the final release of the
802.3x standard has specified the type/length value for MAC Control Frames as 88-08.
Table 37-33. FCT: Flow Control Type Register
Description: This register must be programmed with 0x00_00_88_0
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 0030h
Offset End: 0033h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 0030h
Offset End: 0033h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 0030h
Offset End: 0033h
Size: 32 bits
Default: 00008808h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range
31 16
15 : 00
Bit Acronym
Bit Description
Sticky
RSVD
FCT
Reserved
This register must be programmed with 0x00_00_88_08.
Bit Reset
Value
0000h
8808h
Bit Access
RV
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1451