EP80579 Datasheet, PDF (513/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-130.Offset 88h: EDMA_EMASK - EDMA Error Mask Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:1:0
Offset Start: 88h
Offset End: 88h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07
06
05
04
03
02
01
00
Bit Acronym
Bit Description
Sticky
Descriptor Address Type/Range Error Mask: Mask bit
for error bit 7, 15, 23, and 31 of EDMA_FERR and
EDMA_NERR. This bit is sticky through reset.
DSCPEM 0 = Allow descriptor address type/range error logging and Y
signaling.
1 = Mask descriptor address type/range error logging and
signaling.
Descriptor Address Alignment Error: Mask bit for error
bit 6, 14, 22, and 30 of EDMA_FERR and EDMA_NERR. This
bit is sticky through reset.
DSCPAE 0 = Allow descriptor address alignment error logging and
Y
signaling.
1 = Mask descriptor address alignment error logging and
signaling.
SRCEM
Source Address Type/Range Error: Mask bit for error
bit 5, 13, 21, and 29 of EDMA_FERR and EDMA_NERR. This
bit is sticky through reset.
0 = Allow source address type/range error logging and
Y
signaling.
1 = Mask source address type/range error logging and
signaling.
Reserved Reserved
Y
Destination Address Type/Range Error: Mask bit for
error bit 3, 11, 19, and 27 of EDMA_FERR and
EDMA_NERR. This bit is sticky through reset.
DESTEM 0 = Allow destination address type/range error logging
Y
and signaling.
1 = Mask destination address type/range error logging
and signaling.
Reserved Reserved
Y
Memory Data Parity Error: Mask bit for error bit 1, 9,
17, and 25 of EDMA_FERR and EDMA_NERR. This bit is
MDPARERR ^{sticky through reset.}
Y
0 = Allow memory data parity error logging and signaling.
1 = Mask memory data parity error logging and signaling.
IWERR
Illegal Write Error: Mask bit for error bit 0, 8, 16, and 24
of EDMA_FERR and EDMA_NERR. This bit is sticky through
reset.
Y
0 = Allow illegal write error logging and signaling.
1 = Mask illegal write error logging and signaling.
Bit Reset
Value
0b
0b
0b
0b
0b
0b
0b
0b
Bit Access
RW
RW
RW
RW
RW
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
513