EP80579 Datasheet, PDF (700/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
17.1.3.4 Offset 01AAh: LSTS - Link Status Register
Table 17-18. Offset 01AAh: LSTS - Link Status Register
Description:
View: PCI
BAR: RCBA
Bus:Device:Function: 0:31:0
Offset Start: 01AAh
Offset End: 01ABh
Size: 16 bit
Default: 0041h
Power Well: Core
Bit Range
15 :10
09 :04
03 :00
Bit Acronym
Bit Description
Sticky
Reserved
NLW
LS
Reserved
Negotiated Link Width: Minimum negotiated link width
is a x4 port. The contents of this register are undefined if
the link has not successfully trained.
Link Speed: Link is 2.5 Gbits/s.
Bit Reset
Value
00h
4h
1h
Bit Access
RO
RO
17.1.4
17.1.4.1
TCO Configuration
Offset 3000h: TCTL - TCO Control Register
Table 17-19. Offset 3000h: TCTL - TCO Control Register (Sheet 1 of 2)
Description:
View: IA F
Base Address: RCBA
Offset Start: 3000h
Offset End: 3001h
Size: 8 bit
Default: 0h
Power Well: Core
Bit Range
07
Bit Acronym
Bit Description
Sticky
TCO IRQ Enable:
IE
0 = TCO IRQ is disabled.
1 = TCO IRQ is enabled, as selected by the TCO_IRQ_SEL
field.
Bit Reset
Value
0h
Bit Access
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
700
August 2009
Order Number: 320066-003US