EP80579 Datasheet, PDF (555/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-180.Offset 60h: MSIDR - MSI Data Register (Sheet 2 of 2)
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 60h
Offset End: 61h
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 60h
Offset End: 61h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range Bit Acronym
Bit Description
Destination Mode: Same as bit 2 of MSIAR.
11
DMMSID
0 = Physical
1 = Logical
Sticky
Bit Reset
Value
Bit Access
0b
RW
10 : 08
07 : 00
DELM
IV
Delivery Mode: Same as the corresponding bits in the I/O
Redirection Table for that interrupt.
000= Fixed
001= Lowest Priority
010= SMI/PMI
011= Reserved
100=NMI
101=INIT
110=Reserved
111=ExtINT
Interrupt Vector: Same as the corresponding bits in the
I/O Redirection Table for that interrupt.
0h
RW
00h
RW
16.4.1.42 Offset 64h: PEACAPID - PCI Express* Features Capabilities ID
Register
This register identifies the PCI Express* features capability structure.
Table 16-181.Offset 64h: PEACAPID - PCI Express Features Capabilities ID Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 64h
Offset End: 64h
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 64h
Offset End: 64h
Size: 8 bit
Default: 10h
Power Well: Core
Bit Range Bit Acronym
Bit Description
07 : 00
CAP_ID
This field has the value 10h to identify the CAP_ID
assigned by the PCI SIG for PCI Express* capability
structure.
Sticky
Bit Reset
Value
Bit Access
10h
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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