EP80579 Datasheet, PDF (1315/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
35.11.1.21 Offset E7h: STYP – Signal Target Capability Type Register
Table 35-141.Offset E7h: STYP: Signal Target Capability Type Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: M:7:0
Offset Start: E7h
Offset End: E7h
Size: 8 bit
Default: 01h
Power Well: Core
Bit Range Bit Acronym
Bit Description
07 : 00
STYP
Capability Record Type: Vendor assigned capability
record type (01h, EP80579 signal target capability)
Sticky
Bit Reset
Value
Bit Access
01h
RO
35.11.1.22 Offset E8h: SMIA – Signal Target IA Mask Register
Table 35-142.Offset E8h: SMIA: Signal Target IA Mask Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: M:7:0
Offset Start: E8h
Offset End: E8h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 : 01
00
Bit Acronym
Bit Description
Sticky
Reserved
SMIA
IA mask bit: If set to 1h, an interrupt is sent to the IA as
either an INTx or MSI based on the PCI signaling
configuration when detect IEEE 1588 Interrupt
Bit Reset
Value
0h
0h
Bit Access
RW
RW
35.11.1.23 Offset E9h: Reserved Register
Writing to this register will result in undefined behavior.
35.11.1.24 Offset EAh: Reserved Register
Writing to this register will result in undefined behavior.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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