EP80579 Datasheet, PDF (398/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.1.1.13 Offset 50h: CFG0 - IMCH Configuration 0 Register
MCHCFG consists of IMCH CFG1 in the upper 8 bits and IMCH CFG0 in the lower 8 bits.
Table 16-15. Offset 50h: CFG0- IMCH Configuration 0 Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: 50h
Offset End: 50h
Size: 8 bit
Default: 0Ch
Power Well: Core
Bit Range
07 : 03
02
01
00
Bit Acronym
Bit Description
Sticky
Reserved
IOQD
DRFD
Reserved
Reserved
In-Order Queue Depth: This bit reflects the value
sampled on HA[7]# on the de-assertion of the CPURST#.
It indicates the depth of the CPU bus in-order queue.
0 = HA[7]# has been sampled asserted (e.g., logic one, or
electrical low). The depth of the IOQ is set to one
(e.g., no pipelining on the processor bus). HA[7]#
may be driven low during CPURST# by an external
source.
1 = HA[7]# was sampled as deasserted (e.g. logic zero or
electrical high). The depth of the processor bus in-
order queue is configured to the maximum (e.g., 12).
Deferred Resource Fairness Disable:
0 = Clearing the bit allows the fairness logic to start
working again.
1 = Setting this bit clears the fairness logic for deferred
resources and hold it in reset.
Note: This bit should only be changed in the event that
there is some issue with the fairness logic.
Reserved
Bit Reset
Value
0h
1b
0b
0b
Bit Access
RO
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
398
August 2009
Order Number: 320066-003US