EP80579 Datasheet, PDF (689/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
17.0
17.1
Note:
Bridging and Configuration
Root Complex Memory-Mapped Configuration Register
Details
This section describes all registers and base functionality that are related to
configuration and not a specific interface (such as LPC). It contains the root complex
register block, which describes the behavior of the upstream internal link.
The root complex register block is mapped into memory space using register RCBA (see
Section 19.2.7.1, “Offset F0h: RCBA: Root Complex Base Address Register”). Accesses
in this space must be limited to 32-bit (Dword) quantities. Burst accesses are not
allowed.
Address locations that are not listed are considered reserved register locations. Reads
to reserved registers may return non-zero values. Writes to reserved locations may
cause system failures or undetermined behavior. For more information on the format of
the register description tables that follow in this chapter, see Section 7.1.1, “Register
Description Tables”).
Table 17-1. Bus 0, Device 31, Function 0: Summary of Root Complex Configuration
Registers Mapped Through RCBA Memory BAR (Sheet 1 of 2)
Offset Start Offset End
Register ID - Description
Default
Value
0000h
0004h
0008h
000Ch
000Eh
0010h
0014h
001Ah
0100h
0104h
0110h
0118h
01A0h
01A4h
01A8h
0003h
0007h
000Bh
000Dh
000Fh
0013h
0017h
001Bh
0103h
0107h
0113h
011Fh
01A3h
01A7h
01A9h
“Offset 0000h: VCH - Virtual Channel Capability Header Register” on page 691
10010002h
“Offset 0004h: VCAP1 - Virtual Channel Capability 1 Register” on page 691
0801h
“Offset 0008h: VCAP2 - Virtual Channel Capability 2 Register” on page 692
0001h
“Offset 000Ch: PVC - Port Virtual Channel Control Register” on page 692
0h
“Offset 000Eh: PVS -Port Virtual Channel Status Register” on page 693
0h
“Offset 0010h: V0CAP - Virtual Channel 0 Resource Capability Register” on
page 693
00000001h
“Offset 0014h: V0CTL - Virtual Channel 0 Resource Control Register” on page 694 800000FFh
“Offset 001Ah: V0STS - Virtual Channel 0 Resource Status Register” on page 695 0h
“Offset 0100h: RCTCL - Root Complex Topology Capabilities List Register” on
page 696
1A010005h
“Offset 0104h: ESD - Element Self Description Register” on page 696
00000102h
“Offset 0110h: ULD - Upstream Link Description Register” on page 697
0001h
“Offset 0118h: ULBA - Upstream Link Base Address Register” on page 697
00000000000
00000h
“Offset 01A0h: ILCL - Internal Link Capabilities List Register” on page 698
00010006h
“Offset 01A4h: LCAP - Link Capabilities Register” on page 698
0012441h
“Offset 01A8h: LCTL - Link Control Register” on page 699
0h
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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