EP80579 Datasheet, PDF (877/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 23-72. Errors During Non-DATA FIS Reception
Error Type
Received Disparity Error / Illegal Character (K28.3)
Received Disparity Error / Illegal Character (D)
Creaclecuivlaetde₁d different CRC than received or malformed FIS
Phyready dropping unexpectedly
Illegal FIS length for corresponding FIS type²
Host Controller Behavior
Assume character is correct. Reset disparity
counter. Do not set bus master error bit. Do
not return R_ERR (still check for CRC
errors).
Return R_ERR at end of FIS. Do not set bus
master error bit. (Device will retry)
Return R_ERR at end of FIS. Do not set bus
master error bit. (Device will retry)
Send ALIGNs and return link FSM to IDLE.
Do not set bus master error bit. (Device will
retry)
Return R_ERR at end of FIS. Do not set bus
master error bit. (Device will retry).
Table 23-73. Errors During PIO Data FIS Reception
Error Type
Received Disparity Error/ / Illegal character (K28.3)
Received Disparity Error / Illegal Character (D)
Calculated different CRC than received or malformed FIS
received
Phyready dropping unexpectedly
Length of PIO Data FIS not matching transfer count in
PIO_SETUP FIS
Host Controller Behavior
Assume character is correct. Reset disparity
counter. Do not set bus master error bit. Do
not return R_ERR (still check for CRC errors).
Return R_ERR at end of FIS. Do not set bus
master error bit. (Device will not retry)
Return R_ERR at end of FIS. Do not set bus
master error bit. (Device will not retry)
Send ALIGNs and return link FSM to IDLE. Do
not set bus master error bit. (Device will not
retry)
Return R_ERR at end of FIS. Do not set bus
master error bit. (Device will not retry).
Table 23-74. Errors During DMA Data FIS Reception
Error Type
Host Controller Behavior
Received Disparity Error / Illegal Character (K28.3)
Received Disparity Error / Illegal Character (D)
Assume character is correct. Reset disparity
counter. Do not set bus master error bit. Do
not return R_ERR (still check for CRC
errors).
Return R_ERR at end of FIS. Set the bus
master error bit. (Device will not retry)
Calculated different CRC than received or malformed FIS
received or internal buffer overflows (which could be caused by
device violating HOLD-HOLDA latency)
Phyready dropping unexpectedly
Return R_ERR at end of FIS. Set the bus
master error bit. (Device will not retry)
Send ALIGNs and return link FSM to IDLE.
Set the bus master error bit. (Device will
not retry)
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
877