EP80579 Datasheet, PDF (317/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
12.4.3
12.4.4
12.5
12.5.1
The number of reads issued by each EDMA channel in any given internal arbitration
cycle is dependent upon the number of available cache-line spaces in the data queue,
and upon the configuration of the inbound/outbound arbiter, but is limited to a
maximum of two cache-line requests. The number of writes issued in any given
arbitration cycle is dependent upon the number of cache-lines waiting in the data
queue, and upon the CCR configuration, but is limited to a maximum of two cache-line
requests. The EDMA controller never speculatively issues a write in anticipation of data
returning from the memory subsystem.
I/O Memory to Local Memory
The I/O memory to local memory transfer is not supported.
I/O Memory to I/O Memory
The I/O memory to I/O memory transfer is not supported.
Addressing
Each EDMA is capable of 36-bit addressing on both source and destination interfaces.
Alignment specification is independent for source and destination. Transfers may be
specified to be aligned to any byte boundary except in destination constant address
modes where the granularity is greater than 1-byte.
Each EDMA channel uses direct addressing for both the source and destination
interfaces. There is no internal support for any virtual address translation.
Each EDMA channel will attempt to compensate for misalignment between source and
destination. At a minimum, misalignment will result in decreased performance at either
end of the transfer, where a second read is required prior to the first write, or vice-
versa.
Address Coherence
Each EDMA channel provides support for non-coherent access specification to improve
bandwidth and provide more consistent average latency, as well as to free the FSB for
simultaneous IA-32 core traffic. The source and destination addresses for each DMA
channel may be independently specified on a chain descriptor granularity via bit
settings in the DCR to be either coherent or non-coherent. For non-coherent accesses,
no FSB snoop cycle is issued on behalf of EDMA memory accesses to snoop processor
caches. The software must verify that snoops of IA-32 core caches are not required for
proper system operation prior to setting either of the non-coherent bits in any given
descriptor. Non-coherent accesses are used for un-cacheable memory regions, or for
cacheable regions where software can guarantee no modified state in any IA-32 core
cache by some other means.
The non-coherent attribute further implies relaxed posted write ordering as defined by
PCI/PCI-X. A non-coherent write may pass coherent posted writes en route to memory.
Software should verify that snoops of IA-32 core caches are not required for proper
system operation prior to setting either of the non-coherent bits in the DCR field of any
given descriptor. Software need not take special steps to accommodate the relaxed
ordering behavior, because each channel will only generate a single stream of output
per descriptor, and no ordering is defined between competing I/O subsystem traffic
sources. Non-coherent access may be used for uncacheable memory regions, or for
cacheable regions where software can guarantee the IA-32 core cache state has not
been modified by other means.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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