EP80579 Datasheet, PDF (1027/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
26.6.2.2
Write Policies for Asynchronous DMA
The Asynchronous DMA engine performs writes to the following memory structures:
Table 26-52. Asynchronous DMA Engine Writes
Memory Structure
Asynchronous Queue
Head Overlay
Asynchronous Queue
Head Status Write
Asynchronous qTD
Status Write
In Data
Size (DWORDS)
Comments
Only the 64-bit addressing format is supported.
14
Dwords 0Ch through 43h are written.
3
Dwords 14h through 1Fh are written.
3
Up to 129
Dwords 04h through 0Fh are written. PID Code, IOC, Buffer
Pointer (page 0), and Alt. Next qTD Pointer are rewritten with
the original value.
Data writes are broken down into 16 Dword-aligned chunks.
Asynchronous DMA write policies:
1. The Asynchronous DMA Engine (ADE) will only generate writes after a transaction is
executed on USB. Some important notes associated with this rule are:
a. If the late-start check fails before the transaction is run on the USB ports, then
the USB transaction and the writes are delayed until the next opportunity to
run the asynchronous traffic.
b. The Queue Head Overlay write occurs after the first transaction for a qTD is
completed on the USB interface.
2. Status writes are always performed after In Data writes for the same transaction.
3. Periodic DMA memory accesses may be interleaved at any point with the
Asynchronous DMA memory accesses on IMCH/IICH link.
4. When writing back the qTD information after clearing the Active bit, the EHCI
Specification does not require that the C_Page field is written. However, due to
byte-granular write control, the EHC does write to this field, and the value is not
necessarily the final or incremented C_Page value.
26.7
Data Encoding and Bit Stuffing
See the USB Rev. 2.0 Specification.
26.8
Packet Formats
See the USB Rev. 2.0 Specification.
26.9
USB 2.0 Interrupts and Error Conditions
The EHCI Specification goes into detail on the EHC interrupts and the error conditions
that cause them. All error conditions that the EHC detects can be reported through the
EHCI Interrupt status bits. Only CMI-specific interrupt and error-reporting behavior is
documented in this section. The EHCI Interrupts Section (in the EHCI Specification)
must be read first, followed by this section, to fully comprehend the EHC interrupt and
error-reporting functionality.
• Based on the EHC’s Buffer sizes and buffer management policies, the Data Buffer
Error can never occur.
• Master Abort and Target Abort responses from the system interface on EHC-
initiated read packets will be treated as Fatal Host Errors. The EHC halts when
these conditions are encountered.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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