EP80579 Datasheet, PDF (356/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
13.8
PCI Express Enhanced Configuration Mechanisms
PCI Express extends the configuration space to 4096 bytes per device/function as
compared to 256 bytes allowed by PCI 2.2 configuration space. PCI Express
configuration space is divided into a PCI 2.2 compatible region, which consists of the
first 256 B of a logical device’s configuration space and an extended PCI Express region
which consists of the remaining configuration space. The PCI 2.2 compatible region can
be accessed using either the mechanisms defined in the PCI 2.2 or using the enhanced
PCI Express configuration access mechanism. All changes made using either access
mechanism are equivalent; however, software is not allowed to interleave PCI Express
and PCI access mechanisms to access the configuration registers of devices. The
extended PCI Express region can only be accessed using the enhanced PCI Express
configuration access mechanism.
13.8.1 PCI Express Configuration Transaction Header
The PCI Express Configuration Transaction Header includes an additional four bits for
the Register Number field (ExtendedRegisterAddress[3:0]) to provide additional
configuration space.
Figure 13-6. PCI Express Configuration Transaction Header
13.8.2
+0
+1
+2
+3
76543210 76543210 765432107 6543210
R
Fmt
X0
Type
R
TC
000
Reserved
T E Attr
D P 00
R
Length
0 0 0 0 0 0 0 0 0 01
Requester ID
Tag
Last DW BE 1st DW
0000
BE
Bus Number
Device
Number
Function
Number
Reserved
Ext. Reg.
Address
Register
Number
R
B4494-01
The PCI 2.2 compatible configuration access mechanism uses the same Request format
as the enhanced PCI Express mechanism. For PCI compatible Configuration Requests,
the Extended Register Address field must be all zeros.
To maintain compatibility with PCI configuration addressing mechanisms, system
software must access the enhanced configuration space using Dword operations
(Dword-aligned) only.
Enhanced Configuration Hardware Implications
The IMCH must translate the memory-mapped extended enhanced PCI Express
configuration access cycles from the host processor to PCI Express configuration cycles.
Devices are required to respond to an additional four bits for decoding configuration
register access. Devices must decode the ExtendedRegisterAddress[3:0] field of the
Configuration Request Header. This field is used in conjunction with the Register
Number to specify the Dword address of the register being accessed.
A PCI Express device must be able to operate with basic required functionality in a
legacy environment without requiring access to any extended PCI Express
configuration.
Intel^® EP80579 Integrated Processor Product Line Datasheet
356
August 2009
Order Number: 320066-003US