EP80579 Datasheet, PDF (1592/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
39.6.1.6
Offset 00000014h: Config - CAN Configuration Register
The CAN unit must be configured prior to its use. The following registers define the
effective CAN data rate, CAN data synchronization, and message buffer arbitration.
Note:
Additional information on the CAN data rate settings using time segment1(tseg1), time
segment2(tseg2), and the bit rate are given in Section 39.4.4, “CAN Bit Timing” on
page 1577.
Table 39-11. Offset 00000014h: Config - CAN Configuration Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:4:0
Offset Start: 00000014h
Offset End: 00000017h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:5:0
Offset Start: 00000014h
Offset End: 00000017h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range Bit Acronym
Bit Description
Sticky
31
30 :16
15 :13
12
11 :08
7 :05
4
03 :02
1
0
Reserved Reserved, these bits are always 0
Prescaler (bits[14:0]) for generating the time quantum
which defines the TQ:
cfg_bitrate_14_
0
‘0’:
‘1’:
One
One
time
time
quantum
quantum
equals
equals
1
2
clock
clock
cycle
cycles
32767: One time quantum equals 32768 clock cycles
RSVD
Reserved.
cfg_arbiter
Transmit Buffer Arbiter
‘0’: Round Robin: TxMessage0-1-2-3 etc.
‘1’: Fixed Priority: TxMessage0 is highest, TxMessage2 is
lowest
cfg_tseg1
Time segment 1. Length of the first time segment:
tseg1 = cfg_tseg1 +1
Time segment 1 includes the propagation time.
Cfg_tseg1 = 0 and cfg_tseg1 =1 are not allowed.
cfg_tseg2
Time segment 2. Length of the second time segment:
tseg2 = cfg_tseg2 +1
Time segment 2 includes the propagation time.
Cfg_tseg1 = 0 and cfg_tseg1 =1 are not allowed.
‘0’: After bus off, the CAN must be started ‘by hand’.
auto_restart ‘1’: After bus off, the CAN is restarting automatically after
128 groups of 11 recessive bits
cfg_sjw
Synchronization jump width -
1
sjw <= tseg1 and sjw <=
tseg2
CAN bus bit sampling
sampling_mode ‘0’: One sampling point is used in the receiver path
‘1’: 3 sampling points with majority decision are used
edge_mode
CAN bus synchronization logic
‘0’: Edge from ‘R’ to ‘D’ is used for synchronization
‘1’: Both edges are used
Bit Reset
Value
0b
0h
0h
0b
0h
0h
0b
0h
0b
0b
Bit Access
RO
RW
RW
RW
RW
RW
RW
RW
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
1592
August 2009
Order Number: 320066-003US