EP80579 Datasheet, PDF (772/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
20.2.1.8 Offset 08h: DMA_STATUS - DMA Status Register
Table 20-11. Offset 08h: DMA_STATUS - DMA Status Register
Description:
View: IA F 1^a Base Address: 0000h (IO)
Offset Start: 08h
Offset End: 08h
View: IA F 1 Base Address: 0000h (IO)
Offset Start: 18h
Offset End: 18h
View: IA F 2^b Base Address: 0000h (IO)
Offset Start: D0h
Offset End: D0h
View: IA F 2 Base Address: 0000h (IO)
Offset Start: D1h
Offset End: D1h
Size: 8 bit
Default: XXXXXXXh
Power Well: Core
Bit Range Bit Acronym
Bit Description
Sticky
07 : 04
03 : 00
CRS
CTCS
Channel Request Status: When a valid DMA request is
pending for a channel, the corresponding bit is set to 1.
When a DMA request is not pending for a particular
channel, the corresponding bit is set to 0. The source of
the DREQ may be hardware or a software request.
Note: Channel 4 is the cascade channel, so the request
status of channel 4 is a logical OR of the request
status for channels 0 through 3.
4 Channel 0
5 Channel 1 (5)
6 Channel 2 (6)
7 Channel 3 (7)
Channel Terminal Count Status: When a channel
reaches terminal count (TC), its status bit is set to 1. If TC
has not been reached, the status bit is set to 0. Channel 4
is programmed for cascade, so the TC bit response for
channel 4 is irrelevant:
0 Channel 0
1 Channel 1 (5)
2 Channel 2 (6)
3 Channel 3 (7)
a. View 1 describes the control registers for Channels 0-3.
b. View 2 describes the control registers for Channels 4-7.
Bit Reset
Value
XXXX
XXXX
Bit Access
RO
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
772
August 2009
Order Number: 320066-003US