EP80579 Datasheet, PDF (83/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
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Offset 00000008h: Buffer Status Indicators ........................................................1589
Offset 0000000Ch: ErrorStatus - Error Status Indicators ......................................1590
Offset 00000010h: Command - Operating Modes.................................................1591
Offset 00000014h: Config - CAN Configuration Register .......................................1592
Offset 00000020h: TxMessageControl[0-7] - Transmit Message Control and
Command ....................................................................................................1593
Offset 00000024h: TxMessageID[0-7] - Transmit Message ID ...............................1595
Offset 00000028h: TxMessageDataHigh[0-7] - Transmit Message Data High ...........1596
Offset 0000002Ch: TxMessageDataLow[0-7] - Transmit Message Data Low.............1597
Offset 000000A0h: RxMessageControl[0-15] - Receive Message Command and
Control ........................................................................................................1598
Offset 000000A4h: RxMessageID[0-15] - Receive Message ID...............................1600
Offset 000000A8h: RxMessageDataHigh[0-15] - Receive Message Data High...........1600
Offset 000000ACh: RxMessageDataLow[0-15] - Receive Message Data Low ............1601
Offset 000000B0h: RxMessageAMR[0-15] - Receive Message AMR .........................1601
Offset 000000B4h: RxMessageACR[0-15] - Receive Message ACR..........................1602
Offset 000000B8h: RxMessageAMR_Data[0-15] - Receive Message AMR Data .......1603
Offset 000000BCh: RxMessageACR_Data[0-15] - Receive Message ACR Data..........1604
Bus M, Device 6, Function 0: Summary of SSP CSRs ............................................1606
Offset 00h: SSCR0 - SSP Control Register 0 Details ............................................1607
Offset 04h: SSCR1 - SSP Control Register 1 Details ............................................1610
Motorola* SPI Frame Formats for SPO and SPH Programming ..............................1613
Offset 08h: SSSR - SSP Status Register Details ..................................................1614
Offset 0Ch: SSITR - SSP Interrupt Test Register Details ......................................1617
Offset 10h: SSDR - SSP Data Register Details ....................................................1618
Channel Mapping to Interfaces ..........................................................................1622
Clock Synchronization Protocol Flow...................................................................1625
Transparent Clock Synchronization Protocol Flow .................................................1626
IEEE1588 Version 1 and IEEE1588-2008 PTP Message Formats .............................1628
Message Decoding for V1 .................................................................................1629
Message decoding for IEEE1588-2008 ...............................................................1629
PTP Frame Identification ..................................................................................1632
Timestamping Configurations............................................................................1633
Addend Values ................................................................................................1636
Bus M, Device 7, Function 0: Summary of IEEE 1588 TSYNC CSRs .........................1637
Offset 0000h: TS_Control Register ....................................................................1639
Offset 0004h: TS_Event Register .....................................................................1641
Offset 0008h: TS_Addend Register ..................................................................1643
Offset 000Ch: TS_Accum Register ...................................................................1643
Offset 0010h: TS_Test Register .......................................................................1644
Offset 0014h: TS_PPS_Compare Register .........................................................1646
Offset 0018h: TS_RSysTimeLo Register ............................................................1647
Offset 001Ch: TS_RSysTimeHI Register ............................................................1648
Offset 0020h: TS_SysTimeLo Register ..............................................................1649
Offset 0024h: TS_SysTimeHi Register ..............................................................1650
Offset 0028h: TS_TrgtLo Register ....................................................................1650
Offset 002Ch: TS_TrgtHi Register ....................................................................1651
Offset 0030h: TS_ASMSLo Register .................................................................1652
Offset 0034h: TS_ASMSHi Register ...................................................................1653
Offset 0038h: TS_AMMSLo Register ..................................................................1654
Offset 003Ch: TS_AMMSHi Register ..................................................................1655
Offset 0040h: TS_Ch_Control[0-7] - Time Synchronization Channel Control
Register (Per Ethernet Channel) ........................................................................1656
Offset 0044h: TS_CH_EVENT[0-7] - Time Synchronization Channel Event
Register Per Ethernet Channel) .........................................................................1658
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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