EP80579 Datasheet, PDF (272/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
The IMCH allows programmable memory attributes on 13 legacy memory segments of
various sizes in the 768 Kbyte to 1 Mbyte (C0000h – FFFFFh) and 640 Kbytes to 1
Mbyte address range. Seven Programmable Attribute Map (PAM) registers are used to
support these features. Not all seven of these registers are identical. PAM0 controls
only one segment (high), while PAM[1:6] each control two segments (high and low).
Cache ability of these areas is controlled via the MTRR registers in the processor. The
following two bits apply to both host accesses and PCI initiator accesses to the PAM
areas and are used to specify the memory attributes for each memory segment: These
bits apply to both host accesses and PCI initiator accesses to the PAM areas
RE
Read Enable. When RE = 1, the IA-32 core read accesses to the
corresponding memory segment are claimed by the IMCH and
directed to main memory. Conversely, when RE = 0, the host
read accesses are directed to the IICH’s PCI bus.
WE
Write Enable. When WE = 1, the host write accesses to the
corresponding memory segment are claimed by the IMCH and
directed to main memory. Conversely, when WE = 0, the host
write accesses are directed to the IICH’s PCI bus.
Together, these two bits specify memory attributes (Read-Only, Write Only, Read/Write
and Disabled) for each memory segment. These bits only apply to host-initiated access
to the PAM areas. The IMCH forwards to main memory any PCI Express initiated
accesses to the PAM areas. At the time such PCI Express accesses to the PAM region
may occur, the targeted PAM segment must be programmed to Read/Write. It is illegal
to issue a PCI Express initiated transaction to a PAM region with the associated PAM
register not set to Read/Write.
As an example, consider a BIOS that is implemented on the expansion bus. During the
initialization process, BIOS can be shadowed to main memory to increase system
performance. When BIOS is shadowed to main memory it must be copied to the same
address location. To shadow the BIOS, the attributes for that address range must be
set to Write-Only. The BIOS is shadowed by first doing a read of that address, which is
forwarded to the expansion bus. The host then writes the same address, which is
directed to main memory. After BIOS is completely shadowed, the attributes for that
memory area are changed to Read-Only so that all writes are forwarded to the
expansion bus. Figure 10-4 and Table 10-5 show the PAM registers and the associated
attribute bits.
Intel^® EP80579 Integrated Processor Product Line Datasheet
272
August 2009
Order Number: 320066-003US