EP80579 Datasheet, PDF (1626/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
41.5.1.2.2
Protocol for Transparent Switches
The synchronization protocol flow through a transparent switch is described in
Figure 41-4.
Table 41-3. Transparent Clock Synchronization Protocol Flow
Action
Responsibility
Node Type
Sync Packet
Generate a Sync Packet
SW
Timestamp the Sync packet and store the value in registers (T1)
HW
Timestamp the incoming Sync packet; store the value in a register
(T2); and record the sourceID and sequenceId in registers
HW
Forward the received Sync Packet to the slave
SW
Timestamp the Sync packet and store the value in registers (T2a)
HW
Timestamp the incoming Sync packet; store the value in a register
(T3); and record the sourceID and sequenceId in registers
HW
Follow_Up Packet
Read the timestamp register (T1) and put the value in a Follow_Up
packet and send it.
SW
Forward the received Follow_Up packet, first appending the
Residence Time (RC2) of the previous Sync packet. RC2 being the
delay between receiving the Sync packet (T2) and transmitting the
SW
sync packet (T2a)
Note the timestamp (T1) and the residence time (RC2) from the
received Follow-up message
SW
Delay_Req Packet
Generate a Delay_Req packet and send it
SW
Timestamp the outgoing Delay_Req packet and store in register (T4) HW
Timestamp incoming Delay_Req message; store value (T5); record
sourceID and sequenceID in registers
HW
Forward the received Delay_Req Packet to the master
SW
Timestamp the outgoing Delay_Req packet and store the value in
registers (T5a)
HW
Timestamp incoming Delay_Req message; store value (T6); record
sourceID and sequenceID in registers
HW
Delay_Response Packet
Read timestamp (T6) from register and send back to slave using a
Delay_Response packet
SW
Forward the received Delay_Response packet, first appending the
Residence Time (RC5) of the previous Delay_Req packet. RC5 being
the delay between receiving the Delay_Req packet (T5) and
SW
transmitting the Delay_Req packet (T5a)
Note the timestamp (T6) and the residence time RC5 from received
Delay_Resp packet and calculate the time offset using T1, RC2, T3, SW
T4, RC5 and T6
Master
Master
Transparent
Switch
Transparent
Switch
Transparent
Switch
Slave
Master
Transparent
Switch
Slave
Slave
Slave
Transparent
Switch
Transparent
Switch
Transparent
Switch
Master
Master
Transparent
Switch
Slave
Intel^® EP80579 Integrated Processor Product Line Datasheet
1626
August 2009
Order Number: 320066-003US