EP80579 Datasheet, PDF (283/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
10.6
10.6.1
Note:
Memory Reclaim Background
The following Memory Mapped I/O devices and ranges are typically located below 4
GBytes:
• High BIOS
• H-Seg
• XAPIC
• Local APIC
• FSB Interrupts
• PEA0 through PEA1 M, PM and BAR regions
In previous generation MCH architectures, the physical DRAM memory overlapped by
the logical address space allocated to these Memory Mapped I/O devices was unusable.
In server systems the memory allocated to memory mapped I/O devices could easily
exceed 1 GByte. This creates the possibility of a large amount of physical memory
populated in the system becoming unusable.
The IMCH provides the capability to reclaim the physical memory overlapped by the
Memory Mapped I/O logical address space via remapping physical memory from the
Top of Low Memory (TOLM) boundary up the 4 GBytes boundary (or TOM if less than 4
GBytes) to an equivalent sized logical address range located just above the top of
physical memory
Memory Remapping Algorithm
The IA-32 core is not capable of using the remap capability and care must be taken to
ensure that no addresses sent to the IA-32 core are greater than TOLM in that it will
cause aliasing. The remap capability can be utilized by the AIOC, IICH and PCIe ports.
Terminology clarification:
Physical Address
The address presented to the IMCH is traditionally called a
“physical address,” because Intel architecture processors
contain both segmentation and paging hardware, and all
compatible software differentiates between logical addresses,
virtual addresses, and physical addresses. The algorithm for
remapping addresses presented to the IMCH to reclaim DRAM
address space must be implemented such that the mechanism
is invisible to compatible software.
System Address
The system address applies to the internal IMCH interface to
physical DRAM memory, and is not directly visible to software,
other than through certain internal logging registers used to
store decoded DRAM address information for error isolation.
An incoming address (referred to as a physical address) is checked to see if it falls in
the memory remap window. The bottom of the remap window is defined by the value in
the REMAPBASE register (see Section 16.1.1.31, “Offset C6h: REMAPBASE - Remap
Base Address Register”). The top of the remap window is defined by the value in the
REMAPLIMIT register (Section 16.1.1.32, “Offset C8h: REMAPLIMIT – Remap Limit
Address Register”). An address that falls within this window is remapped to the physical
memory starting at the address defined by the TOLM register.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
283