EP80579 Datasheet, PDF (808/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
22.2.1.2 Offset 04h: GP_IO_SEL1 - GPIO Input/Output Select 1 {31:0}
Register
Table 22-5. Offset 04h: GP_IO_SEL1 - GPIO Input/Output Select 1 {31:0} Register
Description: This register allows setting of input/output direction of the GPIO pins 31-0
View: PCI
Size: 32 bit
BAR: GBA(IO)
Default: E400FFFFh
Bus:Device:Function: 0:31:0
Offset Start: 04h
Offset End: 07h
Power Well: Core^a
Bit Range Bit Acronym
Bit Description
Sticky
31 : 29
28 : 27
26
25 : 24
23
22
21 : 16
15 : 00
GPI_31_29 Always 1. The GPI pins are always inputs.
• Input when in IRQ mode. I/O when in GPIO mode.
0 = The GPIO signal is programmed as an output.
GP_IO_SEL_28_ 1 = The corresponding GPIO signal (if enabled in
27
Table 22-4, “Offset 00h: GPIO_USE_SEL1 - GPIO
Use Select 1 {31:0} Register” on page 807) is
programmed as an input.
GPI_26
Always 1. The GPI pins are always inputs.
• Input when in IRQ mode. I/O when in GPIO mode.
0 = The GPIO mode signal is programmed as an
GP_IO_SEL_25_
24
1
=
output.
The corresponding GPIO mode signal (if enabled in
Table 22-4, “Offset 00h: GPIO_USE_SEL1 - GPIO
Use Select 1 {31:0} Register” on page 807) is
programmed as an input.
GP_IO_23
This GPIO pin is output, when in GPIO mode (reports
0h). Input when used as IRQ (reports 1h)
Reserved Reserved. No corresponding GPIO.
GP_IO_21_16
These GPIO pins are outputs, when in GPIO mode
(reports 00h). Input when used as IRQ (reports 3Fh)
GPI_15_0 Always 1. The GPI pins are always inputs.
a. Core for 0:7, 16:21, 23; Resume for 8:15, 24:31.
Bit Reset
Value
111b
00b
1b
00b
0h
0h
00h
FFFFh
Bit Access
RO
RW
RO
RW
RO
RO
RO
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
808
August 2009
Order Number: 320066-003US