EP80579 Datasheet, PDF (683/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.7.1.6
Offset 14h: NSIVC0RCTL - NSI VC0 Resource Control Register
This register controls the resources associated with PCI Express Virtual Channel 0.
Table 16-353.Offset 14h: NSIVC0RCTL - NSI VC0 Resource Control Register
Description:
View: PCI
BAR: NSIBAR
Bus:Device:Function: 0:0:0
Offset Start: 14h
Offset End: 17h
Size: 32 bit
Default: 800000FFh
Power Well: Core
Bit Range
31
30 : 27
26 : 24
23 : 20
19 : 17
16 : 08
07 : 01
00
Bit Acronym
Bit Description
Sticky
VC0EN
Reserved
VC0ID
Reserved
PARBSEL
Reserved
TCVC0M
TC0VC0M
VC0 Enable: Hardwired to 1. VC0 can never be
disabled.
Reserved
VC0 ID: Assigns a VC ID to the VC resource. For VC0
this is hardwired to 0 and read only.
Reserved
Port Arbitration Select: Configures the VC resource to
provide a particular Port Arbitration service.
Valid value for this field is a number corresponding to
one of the asserted bits in the Port Arbitration Capability
field of the VC resource. Because only bit 0 of that field
is asserted. This field is always programmed to ‘1’.
Reserved
TC/VC0 Map: Indicates the TCs (Traffic Classes) that
are mapped to the VC resource. Bit locations within this
field correspond to TC values. For example, when bit 7
is set in this field, TC7 is mapped to this VC resource.
When more than one bit in this field is set, it indicates
that multiple TCs are mapped to the VC resource. In
order to remove one or more TCs from the TC/VC Map
of an enabled VC, software must ensure that no new or
outstanding transactions with the TC labels are targeted
at the given Link.
TC0/VC0 Map: Traffic Class 0 is always routed to VC0.
Thus is will always read as 1b.
Bit Reset
Value
1b
0h
000b
0h
0h
000h
7Fh
1b
Bit Access
RO
RO
RW
RW
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
683