EP80579 Datasheet, PDF (1287/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
35.9.1.24 Offset E8h: SMIA – Signal Target IA Mask Register
Table 35-84. Offset E8h: SMIA: Signal Target IA Mask Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: M:4:0
Offset Start: E8h
Offset End: E8h
View: PCI 2
BAR: Configuration
Bus:Device:Function: M:5:0
Offset Start: E8h
Offset End: E8h
Size: 8 bit
Default: 0h
Power Well: Core
Bit Range
07 : 02
01
00
Bit Acronym
Bit Description
Sticky
Reserved
SMIA1
SMIA0
IA mask bit: If set to 1h, an interrupt is sent to the IA as
either an INTx or MSI based on the PCI signaling
configuration when detect CANx Parity Interrupt
IA mask bit: If set to 1h, an interrupt is sent to the IA as
either an INTx or MSI based on the PCI signaling
configuration when detect CANx System Interrupt.
Bit Reset
Value
0h
0h
0h
Bit Access
RW
RW
RW
35.9.1.25 Offset E9h: Reserved Register
Writing to this register will result in undefined behavior
35.9.1.26 Offset EAh: Reserved Register
Writing to this register will result in undefined behavior.
35.9.1.27 Offset ECh: SINT – Signal Target Raw Interrupt Register
Table 35-85. Offset ECh: SINT: Signal Target Raw Interrupt Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: M:4:0
Offset Start: ECh
Offset End: ECh
View: PCI 2
BAR: Configuration
Bus:Device:Function: M:5:0
Offset Start: ECh
Offset End: ECh
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range Bit Acronym
Bit Description
07 : 02
01
00
Reserved
SINT1
SINT0
Interrupt: Read-only view of CANx Parity Interrupt
Interrupt: Read-only view of CANx System Interrupt
Sticky
Bit Reset
Value
0h
0h
0h
Bit Access
RO
RO
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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