EP80579 Datasheet, PDF (578/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.4.1.63 Offset 114h: CORERRMSK - Correctable Error Mask Register
The Correctable Error Mask register controls reporting of individual errors by device to
the PCI Express* Root Complex via a PCI Express* error message. A masked error
(respective bit set in mask register) is not reported to the PCI Express* Root Complex
by an individual device. However, masked errors are still logged in the Correctable
Error Status register. There is one mask bit corresponding to every implemented bit in
the Correctable Error Status register. These bits are sticky through reset.
Table 16-202.Offset 114h: CORERRMSK - Correctable Error Mask Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 114h
Offset End: 117h
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 114h
Offset End: 117h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 13
12
11 : 09
08
07
06
05 : 01
00
Bit Acronym
Bit Description
Sticky
Reserved Reserved
Replay Timer Timeout Mask: This bit is sticky through
system reset.
RTTM
0 = Report Replay Timer Timeout error.
Y
1 = Mask Replay Timer timeout error.
Reserved Reserved
REPLAY_NUM Rollover Mask: This bit is sticky through
system reset.
RNRM
0 = Report REPLAY_NUM rollover
Y
1 = Mask REPLAY_NUM rollover.
BDM
Bad DLLP Mask: This bit is sticky through system reset.
0 = Report Bad DLLP error.
Y
1 = Mask Bad DLLP error.
Bad TLP Mask: This bit is sticky through system reset.
BTM
0 = Report Bad TLP error.
Y
1 = Mask Bad TLP error.
Reserved Reserved
REM
Receiver Error Mask: This bit is sticky through system
reset.
0 = Report Receiver error.
Y
1 = Mask Receiver error.
Bit Reset
Value
00000h
0b
000b
0b
0b
0b
0000b
0b
Bit Access
RW
RW
RW
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
578
August 2009
Order Number: 320066-003US