EP80579 Datasheet, PDF (399/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.1.1.14 Offset 51h: IMCH_CFG1 – IMCH Configuration 1 Register
Table 16-16. Offset 51h: IMCH_CFG1 – IMCH Configuration 1 Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: 51h
Offset End: 51h
Size: 8 bit
Default: 00000h
Power Well: Core
Bit Range
07 : 05
04 : 00
Bit Acronym
Bit Description
Sticky
NSG
Reserved
Number of Stop Grant Cycles: Number of Stop Grant
transactions expected on the FSB bus before a Req_C2
packet is sent to the IICH. This field is programmed by the
BIOS after it has enumerated the processors and before it
has enabled Stop Clock generation in the IICH. Once this
field has been set, it must not be modified. Note that each
enabled thread within each CPU generates Stop Grant
Acknowledge transactions.
Note: This register is read/write and not write-once as in
some implementations.
Encoding Description
0 0 0 NSI Stop Grant generated after 1 FSB Stop Grant
0 0 1 NSI Stop Grant generated after 2 FSB Stop Grant
0 1 0 NSI Stop Grant generated after 3 FSB Stop Grant
0 1 1 NSI Stop Grant generated after 4 FSB Stop Grant
1 0 0 NSI Stop Grant generated after 5 FSB Stop Grant
1 0 1 NSI Stop Grant generated after 6 FSB Stop Grant
1 1 0 NSI Stop Grant generated after 7 FSB Stop Grant
1 1 1 NSI Stop Grant generated after 8 FSB Stop Grant
Reserved
Bit Reset
Value
000b
00000b
Bit Access
RW
16.1.1.15 Offset 53h: CFGNS1 - Configuration 1 Register
This register contains IMCH control bits that are not sticky.
Table 16-17. Offset 53h: CFGNS1 - Configuration 1 (Non-Sticky) Register (Sheet 1 of 2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: 53h
Offset End: 53h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 : 02
01
Bit Acronym
Bit Description
Sticky
Reserved
THWO
Reserved
Throttled-Write Occurred:
0 = Writing a zero clears this bit.
1 = This bit is set by hardware when a write is throttled.
This happens when the maximum allowed number of
writes has been reached during a time-slice and there
is at least one more write to be completed.
Bit Reset
Value
000b
0b
Bit Access
RW0C
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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