EP80579 Datasheet, PDF (165/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
IICH Signals
Inputs
VRMPWRGD - Voltage Regulator PowerGood: This signal is directly connected
to the platform signal, CPU_VRD_PWR_GD and signifies that the voltage
regulator is stable.
PWROK - IICH Power Okay: This signal is directly connected to the platform
signal, SYS_PWR_OK. When asserted, PWROK is an indication to the IICH that
power has been stable for at least 99 ms and that PCICLK has been stable for
at least 1 mS. PWROK can be driven asynchronously. When PWROK is inactive,
the IICH asserts PLTRST#.
SYS_RESET# - System Reset: This signal initiates a system reset and causes
PLTRST# to go active. SYS_RESET# must be asserted for at least 100ms.
System reset cannot occur again until SYS_RESET# has been detected
inactive, and the system is back to a full S0 state with PLTRST# inactive. If bit
3 of the Reset Control Register is set then the assertion of SYS_RESET# will
result in a full power cycle reset.
RSMRST# - Resume Well Reset: This signal resets the IICH resume power
plane logic when power is reapplied after a power failure. If the AFTERG3_EN
bit in the General Power Management Configuration 3 Register (D31 F0 Offset
A4) is set to 0, IICH transitions the system from G3 (mechanical off) to S0
state and causes the assertion of the PLTRST# output. If AFTERG3_EN is 1, the
system will transition to S5 state.
RTEST# - RTC Well Test: This signal is tied to the platform RTCRST# signal.
Normally it is held high (to VccRTC), but can be driven low on the tester or
motherboard to test the RTC well. RTEST# resets some bits in the RTC well that
are otherwise not reset by PLTRST# or RSMRST#. An external RC circuit on the
RTCRST# signal creates a time delay such that RTCRST# will go high some
time after the battery voltage is valid. The RC time delay must be in the 10-20
ms range. This allows detection when a new battery has been installed. Unless
entering a XOR Chain test mode, the RTEST# input must always be high when
all other non-RTC power planes are on.
Outputs
CPUPWRGD - CPU PowerGood: This signal is the logical AND of the IICH
VRMPWRGD and PWROK input signals. This signal is connected to the
processor's powergood input to indicate when the processor power is valid.
PLTRST# - Platform Reset: This signal is asserted by SYS_RESET#,
RSMRESET#, or software. The IICH asserts PLTRST# to reset devices on the
platform (e.g., SIO, FWH, LAN, IMCH, IDE, TPM, etc.) during power-up
(CPU_PWRGD de-asserted) and when software initiates a hard reset sequence
through the Reset Control register. The IICH drives PLTRST# active a minimum
of 1 ms when initiated through the Reset Control register. The IICH de-asserts
PLTRST# a minimum of 1 ms after CPU_PWRGD is driven high.
PCIRST# - PCI Reset: This is the secondary PCI bus reset signal. This signal is
asserted a small number of PCI clocks after PLTRST# or can be asserted
independently by the Secondary Bus Reset bit.
6.1.2.3.2
IMCH
IMCH plays a crucial role in the reset sequence for IA-32 core. IMCH receives the
powergood signal (SYS_PWR_OK) from the platform. The IICH PLTRST# drives the
IMCH RSTIN# input. IMCH drives the CPURST# (internal signal) while it is in the reset.
IMCH works with IICH to initialize the NSI link between IICH and IMCH. Once the
central reset (PLTRST#) is de-asserted, IMCH de-asserts the CPURST# (internal
signal).
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
165