EP80579 Datasheet, PDF (1030/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
• Host-Initiated Write Data
• Read Completion Data to the EHC
When any of these three errors are detected and the Parity Error Response bit is set in
the USB 2.0 function, the EHC immediately sets the Host Error bit to ‘1’ and clears the
Run/Stop bit to ‘0’. At most, one more packet completes on the high-speed USB ports
after this occurs (this packet will not contain, or be based upon, the data containing the
host error). When that packet is completed, the HCHalted bit is set to a ‘1’. Once the
Host Error bit has been set, the Run/Stop bit can not be set by software until after the
HCRESET is generated by software and completed by the EHC, which lasts for multiple
milliseconds. The EHC will still accept host-initiated cycles as a target after the
HCHalted bit has been set.
It is recommended that software reboot in the event of a parity error because the error
could be an indication of other system hardware problems.
26.10 USB 2.0 Power Management
26.10.1
Pause Feature
This feature allows platforms to dynamically enter low-power states during brief
periods when the system is idle (i.e., between keystrokes). This is useful for enabling
power management features like Enhanced Intel SpeedStep Technology (EIST). The
policies for entering these states typically are based on the recent history of system
bus activity to incrementally enter deeper power management states. Normally, when
the EHC is enabled, it regularly accesses main memory while traversing the DMA
schedules looking for work to do; this activity is viewed by the power management
software as a non-idle system, thus preventing the power managed states to be
entered. Suspending all of the enabled ports can prevent the memory accesses from
occurring, but there is an inherent latency overhead with entering and exiting the
suspended state on the USB ports that makes this unacceptable for the purpose of
dynamic power management. As a result, the EHCI software drivers are allowed to
pause the EHC’s DMA engines when it knows that the traffic patterns of the attached
devices can afford the delay. The pause only prevents the EHC from generating
memory accesses; the SOF packets continue to be generated on the USB ports (unlike
the suspended state).
The expected sequence of events for the Pause Feature is:
1. When starting the DMA engines for the first time, the enable bits are set at the
same time as, or after, the Run bit is set. However, the EHC should be capable of
handling the Run bit set to 0 while one or both of the enable bits are 1; this may
happen, for example, when the hardware halts the DMA due to an error. The enable
bits may be set to 1 by different writes to the Command Register. The EHC takes
the following actions when the enable bits are set by software:
a. The corresponding Asynch/Periodic Schedule Status bit(s) is (are) immediately
set to 1.
b. If the Asynch Enable bit is set, the first queue head in the asynchronous
schedule is immediately fetched (if the Bus Master Enable bit in Configuration
space is set).
c. If the Periodic Enable bit is set, then the periodic frame list entry is fetched (if
the Bus Master Enable bit in Configuration space is set) on the next internal
trigger point, which may be up to 1 ms later.
2. Before clearing a Schedule Enable bit, software reads the USB 2.0 Status register
to make sure that the corresponding Schedule Status bit has been set.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1030
August 2009
Order Number: 320066-003US