EP80579 Datasheet, PDF (319/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Figure 12-5. Source and Destination in Increment Mode Transfer
MSB
64-bit Source
7
6
15
14
Data Block
Transfer
Memory
5
4
3
13
12
11
20
19
2
1
10
9
18
17
LSB
ADDRESS
A000 0200H
8
A000 0208H
16
A000 0210H
1
9
64-bit Destination
17
Programmed Values
EDMACTL 0000 0088H
SUAR/SAR _{A000 0201H}
DUAR/DAR 4001 0307H
TCR _{0000 0014H}
DCR 0000 001FH
4001 0300H
8
7
6
5
4
3
2
4001 0308H
16
15
14
13
12
11
10
4001 0310H
20
19
18
4001 0318H
10
byte number
Bus Operation
SOURCE
QWORD load@A0000200
QWORD load@A0000208
QWORD load@A0000210
DESTINATION
Byte store@40010307
QWORD store@40010308
QWORD store@40010310
3-Byte store@40010318
B4484-01
12.5.2.2
Decrement/Byte Reversal Mode
Decrement/byte reversal mode is useful when an entire data stream needs to be
reversed at the byte level. This must not be confused with endian swapping, as this
implies a specific word size. In this mode, the source and destination are specified
down to the byte address. The source data is read in reverse order and written to the
destination in increasing order. Transfers can be memory to memory or memory to
memory mapped I/O. Figure 12-6 illustrates a memory to memory data transfer
between unaligned 64-bit, source and destination addresses when the source is in
decrement mode and the destination is in increment mode.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
319