EP80579 Datasheet, PDF (173/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 6-5. Powergood Reset Timings
Timing
Description
T_ab
VRMPWRGD/ CPU_VRD_PWR_GD assertion to Reference Clock Stable
T_ac
VRMPWRGD/ CPU_VRD_PWR_GD assertion to SYS_PWR_OK (platform signal)
assertion
SYS_PWR_OK (platform signal) assertion to CPU_PWRGD assertion
T_cd
(CPU_PWRGD is logical AND of VRMPWRGD/ CPU_VRD_PWR_GD and
SYS_PWR_OK)
Tdf CPU_PWRGD assertion to PLTRST# de-assertion
Tfi RSTIN# deassertion to CPURST# (internal signal) de-assertion
Tij
CPURST# (internal signal) de-assertion to POC invalid
2 ms
99 ms
Value
logic delay
1 ms
1 ms + CPU_RST_DONE
transaction delay (max 10,000 PCI-
e clocks) + CPU_RST_DONE
capture timer (min 2000 reference
clocks)
2 reference clocks
Figure 6-7. Hard Reset Sequence
Reference Clock
SYS_PWR_OK/PWROK/
PWRGD/CPU_PWRGD
SYS_RESET#
PLTRST#/RSTIN#
CPU Power-On
Configuration
CPURST#
a
d
gh
B6549-01
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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