EP80579 Datasheet, PDF (1478/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.4.2
Note:
FCRTL: Flow Control Receive Threshold Low Register
This register contains the receive threshold used to determine when to send an XON
packet, counting in units of bytes. The lower 3 bits must be programmed to 0 (8B
granularity). Whenever hardware crosses the receive high threshold (becoming more
full), and then crosses the receive low threshold, then hardware will transmits an XON
frame (if enabled with FCRTL.XONE).
Flow control reception/transmission are negotiated capabilities by the Auto-Negotiation
process. When the device is manually configured, flow control operation is determined
by the CTRL.RFCE & CTRL.TFCE.
Table 37-51. FCRTL: Flow Control Receive Threshold Low Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 2160h
Offset End: 2163h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 2160h
Offset End: 2163h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 2160h
Offset End: 2163h
Size: 32 bits
Default: 00000000h
GbE0: Core
Power Well: Gbe1/2:
Core
Bit Range
31
30 : 16
15 : 03
02 : 00
Bit Acronym
Bit Description
Sticky
XONE
Rsvd
RTL
0
XON Enable
0b = Disabled.
1b = Enabled.
When set, enables the Ethernet controller to transmit XON
packets based on receive FIFO crosses FCRTL.RTL
threshold value, or based on external pins XOFF and XON.
See Section 37.6.4.3, “FCRTH – Flow Control Receive
Threshold High Register” on page 1479
Reserved
Receive Threshold Low. FIFO low water mark for flow
control transmission.
Writes are ignored, reads return 0.
Bit Reset
Value
0h
0h
0h
0h
Bit Access
RW
RV
RW
RV
Intel^® EP80579 Integrated Processor Product Line Datasheet
1478
August 2009
Order Number: 320066-003US