EP80579 Datasheet, PDF (1047/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
27.3
Warning:
Note:
27.3.1
Note:
Power Management Register Details
This section shows the power management registers. The power management registers
are distributed within the PCI Device 31: Function 0 space, as well as a separate I/O
range. Each register is described below. Unless otherwise indicated, bits are in the main
(core) power well.
Bits not explicitly defined in each register are assumed to be reserved.
Address locations that are not listed are considered reserved register locations. Reads
to reserved registers my return on-zero values are read only. Writes to reserved
locations may cause system failure and unpredictable behavior.
Reserved bits are read only.
Power Management PCI Configuration Registers
For more information on the format of the register description tables that follow in this
chapter, see Section 7.1.1, “Register Description Tables” on page 183).
Table 27-2. Bus 0, Device 31, Function 0: Summary of LPC Interface Power Management
PCI Configuration Registers
Offset Start Offset End
Register ID - Description
Default
Value
A0h
A0h
“Offset A0h: GEN_PMCON_1 - General PM Configuration 1 Register” on page 1048 0200h
A2h
A2h
“Offset A2h: GEN_PMCON_2 - General PM Configuration 2 Register” on page 1049 00h
A4h
A4h
“Offset A4h: GEN_PMCON_3 - General PM Configuration 3 Register” on page 1051 00h
B8h
BBh
“Offset B8h: GPI_ROUT - GPI Routing Control Register” on page 1053
00000000h
27.3.1.1 Offset A0h: GEN_PMCON_1 - General PM Configuration 1 Register
Table 27-3. Offset A0h: GEN_PMCON_1 - General PM Configuration 1 Register (Sheet 1 of
Description:
View: PCI
Size: 16 bit
BAR: Configuration
Default: 0200h
Bus:Device:Function: 0:31:0
Offset Start: A0h
Offset End: A0h
Power Well: Core^a
Bit Range Bit Acronym
Bit Description
Sticky
15 : 11
10
09
Reserved Reserved
This bit acts as a global enable for the SCI associated with
the PCI Express* ports.
BIOS_PCI_EXP 0 = The various PCI Express* ports and cannot cause the
_EN
PCI_EXP_STS bit to go active.
1 = The various PCI Express* ports and can cause the
PCI_EXP_STS bit to go active.
This bit indicates the current state of the PWRBTN# signal.
PWRBTN_LVL 0 = Low
1 = High
Bit Reset
Value
0h
0h
1
Bit Access
RW
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1047