EP80579 Datasheet, PDF (531/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-144.Offset 06h: PCISTS - PCI Status Register (Sheet 2 of 2)
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 06h
Offset End: 07h
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 06h
Offset End: 07h
Size: 16 bit
Default: 0010h
Power Well: Core
Bit Range
06
05
04
03
02 : 00
Bit Acronym
Bit Description
Sticky
Reserved
C66M
CAPL
INTXS
Reserved
Reserved
Capable 66MHz: Not Applicable
Capabilities List: Hardwired to 1 to indicate the presence
of an Extended Capability List item.
INTx Status: This bit does not get set for interrupts
forwarded up from downstream devices, or for messages
converted to interrupts by the root port. The INTx
Assertion Disable bit has no effect on the setting of this bit.
This bit is not set for an MSI.
0 = An INTx interrupt is not pending internal to this
device.
1 = An INTx interrupt is pending internal to this device.
Reserved
Bit Reset
Value
0b
0b
1b
0b
00h
Bit Access
RO
RO
RO
16.4.1.6
Offset 08h: RID - Revision Identification Register
This register contains the revision number of the device.
Table 16-145.Offset 08h: RID - Revision Identification Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 08h
Offset End: 08h
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 08h
Offset End: 08h
Size: 8 bit
Default: Variable
Power Well: Core
Bit Range
07 : 00
Bit Acronym
Bit Description
Revision Identification Number: This value indicates
RID
the revision identification number for the device 2. It is
always the same as the value in Device 0 RID.
Sticky
Bit Reset
Value
Variable
Bit Access
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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