EP80579 Datasheet, PDF (1893/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
49.5.14.4 TDM AC Characteristics
49.5.14.4.1 Transmit and Receive Timings
Table 49-87. TDM, Serial Timings Values
Symbol
Parameter
Min
Max
Units Notes
T₁
Setup time of TX_FRAME, RX_FRAME, and RX_DATA_IN prior to the rising
edge of clock
5
ns 1, 2, 3
T₂
Hold time of TX_FRAME, RX_FRAME, and RX_DATA_IN after the rising
edge of clock
0
ns 1, 2, 3
T₃
Setup time of TX_FRAME, RX_FRAME, and RX_DATA_IN prior to the
falling edge of clock
5
ns 1, 2, 3
T₄
Hold time of TX_FRAME, RX_FRAME, and RX_DATA_IN after the falling
edge of clock
0
ns 1, 2, 3
T₅
Rising edge of clock to output delay for TX_FRAME, RX_FRAME, and
TX_DATA_OUT
15
ns
1, 4
T₆
Falling edge of clock to output delay for TX_FRAME, RX_FRAME, and
TX_DATA_OUT
15
ns 1, 3, 4
T₇
Output Hold Delay after rising edge of final clock for TX_FRAME,
RX_FRAME, and TX_DATA_OUT
0
ns 1, 3, 4
T₈
Output Hold Delay after falling edge of final clock for TX_FRAME,
RX_FRAME, and TX_DATA_OUT
0
ns 1, 3, 4
T₉
TX_CLK period and RX_CLK period
1/
8.192 MHz
1/
512 kHz
ns
5, 6
Notes:
1.
TX_CLK and RX_CLK may be coming from external independent sources or being driven by the EP80579. The signals are
shown to be synchronous for illustrative purposes and are not required to be synchronous.
2.
Applicable to when the RX_FRAME and TX_FRAME signals are being driven by an external source as inputs into the
EP80579. Always applicable to RX_DATA_IN.
3.
The RX_FRAME and TX_FRAME can be configured to accept data on the rising or falling edge of the given reference clock.
RX_FRAME and RX_DATA_IN signals are synchronous to RX_CLK and TX_FRAME and TX_DATA_OUT signals are
synchronous to the TX_CLK.
4.
Applicable to when the RX_FRAME and TX_FRAME signals are being driven by the EP80579 to an external source. Always
applicable to TX_DATA_OUT.
5.
The TX_CLK can be configured to be driven by an external source or be driven by the EP80579. The slowest clock speed
that can be accepted or driven is 512 kHz. The maximum clock speed that can be accepted or driven is 8.192 MHz. The
clock duty cycle accepted is 50/50 + 20%.
6.
Guaranteed by design. These values are typical values seen for this process, but not measured during production testing.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1893