EP80579 Datasheet, PDF (682/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.7.1.4 Offset 0Ch: NSIPVCCTL - NSI Port VC Control Register
Table 16-351.Offset 0Ch: NSIPVCCTL - NSI Port VC Control Register
Description:
View: PCI
BAR: NSIBAR
Bus:Device:Function: 0:0:0
Offset Start: 0Ch
Offset End: 0Dh
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15 : 04
03 : 01
00
Bit Acronym
Bit Description
Sticky
Reserved
VCARBSEL
Reserved
Reserved
VC Arbitration Select: This field is programmed by
software to the only possible value as indicated in the
VC Arbitration Capability field. The value 000b when
written to this field indicates the VC arbitration scheme
is hardware fixed (in the root complex).
This field cannot be modified when more than one VC in
the LPVC group is enabled.
Reserved
Bit Reset
Value
000h
000b
0b
Bit Access
RW
16.7.1.5 Offset 10h: NSIVC0RCAP - NSI VC0 Resource Capability Register
Table 16-352.Offset 10h: NSIVC0RCAP - NSI VC0 Resource Capability Register
Description:
View: PCI
BAR: NSIBAR
Bus:Device:Function: 0:0:0
Offset Start: 10h
Offset End: 13h
Size: 32 bit
Default: 00000001h
Power Well: Core
Bit Range
31 : 16
15
14 : 08
07 : 00
Bit Acronym
Bit Description
Sticky
Reserved
RSNPT
Reserved
PARBC
Reserved
Reject Snoop Transactions:
0 = Transactions with or without the No Snoop bit set
within the TLP header are allowed on this VC.
1 = Any transaction without the No Snoop bit set within
the TLP header is rejected as an Unsupported
Request.
Reserved
Port Arbitration Capability: Having only bit 0 set
indicates that the only supported arbitration scheme for
this VC is non-configurable hardware-fixed.
Bit Reset
Value
00h
0b
00h
01h
Bit Access
RO
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
682
August 2009
Order Number: 320066-003US