EP80579 Datasheet, PDF (1225/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
34.2.2.21 Offset 24h: PMBASE – Prefetchable Memory Base Register
Note:
Prefetchable memory space is not used by AIOC in the EP80579. BIOS and
enumeration software must be checked to make sure these default values are never
modified to enable prefetchable memory space. Writing to this register can result in
undefined behavior.
Table 34-23. Offset 24h: PMASE: Prefetchable Memory Base Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:4:0
Offset Start: 24h
Offset End: 25h
Size: 16 bit
Default: FFF1H
Power Well: Core
Bit Range
15 : 04
03 : 01
0
Bit Acronym
Bit Description
Sticky
PMBASE
MAMB
MBAUE
These bits correspond to address bits [31:20] of the
transaction.
Memory Addressing Mode.
0 = Disabled
1 = Enabled. Base address is further defined by the bits of
the memory base upper register
Bit Reset
Value
FFFh
0h
1
Bit Access
RW
RO
RO
34.2.2.22 Offset 26h: PMLIMIT – Prefetchable Memory Limit Register
Note:
Prefetchable memory space is not used by AIOC in the EP80579. BIOS and
enumeration software must be checked to make sure these default values are never
modified to enable prefetchable memory space. Writing to this register can result in
undefined behavior.
Table 34-24. Offset 26h: PMLIMIT: Prefetchable Memory Limit Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:4:0
Offset Start: 26h
Offset End: 27h
Size: 16 bit
Default: 1H
Power Well: Core
Bit Range
15 : 04
03 : 01
0
Bit Acronym
Bit Description
Sticky
MEML
MAML
MLAUE
These bits correspond to address bits [31:20] of the
transaction.
Memory Addressing Mode.
0 = Disabled
1 = Enabled. Base address is further defined by the bits of
the memory base upper register
Bit Reset
Value
0h
0h
1
Bit Access
RW
RO
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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