EP80579 Datasheet, PDF (1361/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
• Writing RDTR with its high order bit 1 forces an explicit flush of any partial cache
lines worth of consumed descriptors. Hardware writes all used descriptors to
memory and updates the globally visible value of the RDH head pointer.
Figure 37-11 further describes the Packet Delay Timer operation, in general.
Figure 37-11.Packet Delay Timer operation illustrated with a state diagram
Initial State
packet received & xferred
Idle
to host mem
Restart Count
other receive
timer interrupt
Running
Restart Count
packet received & xfer to
host memory
Generate
Int
Timer expires
Figure 37-12, Figure 37-13, and Figure 37-14 illustrate the uses of the two timers.
Figure 37-12.Case A: Using only an Absolute Timer
Absolute timer value
Pkt1 Pkt2 Pkt3
Pkt4
Interrupt Generated due to pkt #1
To use only the absolute timer the RDTR must be set to a value greater than or equal to the RADV.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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