EP80579 Datasheet, PDF (1450/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.2.8
Note:
Note:
Note:
FCAH – Flow Control Address High Register
Flow control packets are defined by 802.3X to be either a unique multicast address or
the station address with the EtherType field indicating PAUSE. The FCAH and FCAL
registers provide the value hardware compares incoming packets against to determine
that it should PAUSE its output. This register contains the upper bits of the internal 48
bit Flow Control Ethernet address.
Any packet matching the contents of {FCAH, FCAL, FCT} when CTRL.RFCE is set will be
acted on by the EP80579’s GbE. Whether flow control packets are passed to the
software depends on the state of the RCTL.DPF bit and whether the packet matches
any of the normal filters.
At the time of the original implementation, the flow control multicast address was not
defined and thus hardware provided programmability. Since then, the final release of
the 802.3x standard has reserved the following multicast address for MAC Control
Frames: 01-80-C2-00-00-01.
This register MUST be written by software with the appropriate value for the MAC to
behave properly.
Table 37-32. FCAH: Flow Control Address High Register
Description:
This register must
0x00000100.
be
programmed
with
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 002Ch
Offset End: 002Fh
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 002Ch
Offset End: 002Fh
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 002Ch
Offset End: 002Fh
Size: 32 bits
Default: 00000100h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range
31 16
15 : 00
Bit Acronym
Bit Description
Sticky
RSVD
FCAH
Reserved
This register must be programmed with 0x00_00_01_00.
Bit Reset
Value
0
0100h
Bit Access
RV
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
1450
August 2009
Order Number: 320066-003US