EP80579 Datasheet, PDF (435/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.1.1.43 Offset 7Ch: DRC – DRAM Controller Mode Register
This register controls the mode of the DRAM controller.
Table 16-47. Offset 7Ch: DRC - DRAM Controller Mode Register (Sheet 1 of 2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: 7Ch
Offset End: 7Fh
Size: 32 bit
Default: 00000002h
Power Well: Core
Bit Range
31 :31
Bit Acronym
Bit Description
Sticky
CKE1
This bit controls the value that will be driven on the CKE[1]
pin. Note however that CKEPNM bit in this CSR can
override and force low the state of both CKE[1:0] pins
regardless of the state of this bit.
BIOS can write to this CSR bit to directly control the state
of the CKE pin.
Y
HW will update the state of this bit based on self-refresh
exit command.
Bit Reset
Value
0b
Bit Access
RW
0 Drive CKE[1] low, de-activates DRAM devices
1 Drive CKE[1] asserted, activates DRAM devices
This bit controls the value that will be driven on the CKE[0]
pin. Note however that CKEPNM bit in this CSR can
override and force low the state of both CKE[1:0] pins
regardless of the state of this bit.
BIOS can write to this CSR bit to directly control the state
30 30
CKE0
of the CKE pin.
Y
0b
RW
HW will update the state of this bit based on self-refresh
exit command.
0 Drive CKE[0] low, de-activates DRAM devices
1 Drive CKE[0] asserted, activates DRAM devices
0 = Initialization Complete: This bit is used for
communication of software state between the
29 29
IC
memory controller and the BIOS. DRAM interface has N
0b
RW
not been initialized.
1 = DRAM interface has been initialized.
28 :22
Reserved Reserved
N
0000000b
RO
DRAM Data Integrity Mode: These bits select DRAM data
integrity modes. When in non-ECC mode no ECC
correction is done and no ECC errors are logged in the
FERR/NERR registers.
21 :20
DDIM
00 Non-ECC mode
N
00b
RW
01 ECC enabled
10 Reserved
11 Reserved
19 :14
Reserved Reserved
N
0b
RO
Command/address hold disable
Disabling hold will allow the address and bank address pins
13
HLDDIS
to revert to all zeros during idle cycles. When hlddis is
clear, the addresses retain the value of the last non-idle
Y
0b
RW
command cycle in order to reduce switching on the bus.
0 = disabled, 1 enabled
DDR Command/address pin output disable:
12
CADIS
This bit controls Address, bank address, CAS, RAS, WE.
Y
0b
RW
0 = Enabled
1 = Disabled
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
435